aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/usrp/b100/io_impl.cpp
diff options
context:
space:
mode:
authorJosh Blum <josh@joshknows.com>2011-06-29 21:16:28 -0700
committerJosh Blum <josh@joshknows.com>2011-06-29 21:16:28 -0700
commitba088e27b054ddec8e5ec05f53da113f92c2be07 (patch)
tree6137e759e0d6bebc08d3eaa2ea9334738615986c /host/lib/usrp/b100/io_impl.cpp
parent11539ef6f690b4ebd69485be9a61f5422d8cdc99 (diff)
downloaduhd-ba088e27b054ddec8e5ec05f53da113f92c2be07.tar.gz
uhd-ba088e27b054ddec8e5ec05f53da113f92c2be07.tar.bz2
uhd-ba088e27b054ddec8e5ec05f53da113f92c2be07.zip
b100: got b100 into the properties tree like usrp2
Diffstat (limited to 'host/lib/usrp/b100/io_impl.cpp')
-rw-r--r--host/lib/usrp/b100/io_impl.cpp155
1 files changed, 92 insertions, 63 deletions
diff --git a/host/lib/usrp/b100/io_impl.cpp b/host/lib/usrp/b100/io_impl.cpp
index 5377c43d5..00993ab41 100644
--- a/host/lib/usrp/b100/io_impl.cpp
+++ b/host/lib/usrp/b100/io_impl.cpp
@@ -20,8 +20,6 @@
#include "usrp_commands.h"
#include "b100_impl.hpp"
#include "b100_regs.hpp"
-#include <uhd/usrp/dsp_utils.hpp>
-#include <uhd/usrp/dsp_props.hpp>
#include <uhd/utils/thread_priority.hpp>
#include <uhd/transport/bounded_buffer.hpp>
#include <boost/bind.hpp>
@@ -31,7 +29,6 @@
#include <boost/thread.hpp>
#include <uhd/utils/msg.hpp>
#include <uhd/utils/log.hpp>
-#include <iostream>
using namespace uhd;
using namespace uhd::usrp;
@@ -42,10 +39,10 @@ namespace asio = boost::asio;
* IO Implementation Details
**********************************************************************/
struct b100_impl::io_impl{
- io_impl(zero_copy_if::sptr data_transport):
+ io_impl(zero_copy_if::sptr data_transport, const size_t recv_width):
data_transport(data_transport)
{
- for (size_t i = 0; i < B100_NUM_RX_DSPS; i++){
+ for (size_t i = 0; i < recv_width; i++){
typedef bounded_buffer<managed_recv_buffer::sptr> buffs_queue_type;
_buffs_queue.push_back(new buffs_queue_type(data_transport->get_num_recv_frames()));
}
@@ -76,72 +73,125 @@ struct b100_impl::io_impl{
//check the stream id to know which channel
const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
- const size_t rx_index = uhd::wtohx(vrt_hdr[1]) - B100_DSP_SID_BASE;
+ const size_t rx_index = uhd::wtohx(vrt_hdr[1]) - B100_RX_SID_BASE;
if (rx_index == index) return buff; //got expected message
//otherwise queue and try again
- if (rx_index < B100_NUM_RX_DSPS) _buffs_queue[rx_index]->push_with_pop_on_full(buff);
+ if (rx_index < _buffs_queue.size()) _buffs_queue[rx_index]->push_with_pop_on_full(buff);
else UHD_MSG(error) << "Got a data packet with known SID " << uhd::wtohx(vrt_hdr[1]) << std::endl;
}
}
sph::recv_packet_handler recv_handler;
sph::send_packet_handler send_handler;
- bool continuous_streaming;
};
/***********************************************************************
* Initialize internals within this file
**********************************************************************/
void b100_impl::io_init(void){
- _iface->reset_gpif(6);
- _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport));
+ //setup rx otw type
+ _rx_otw_type.width = 16;
+ _rx_otw_type.shift = 0;
+ _rx_otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN;
+
+ //setup tx otw type
+ _tx_otw_type.width = 16;
+ _tx_otw_type.shift = 0;
+ _tx_otw_type.byteorder = uhd::otw_type_t::BO_BIG_ENDIAN;
//set the expected packet size in USB frames
- _iface->poke32(B100_REG_MISC_RX_LEN, 4);
+ _fpga_ctrl->poke32(B100_REG_MISC_RX_LEN, 4);
+
+ //create new io impl
+ _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport, _rx_dsps.size()));
- update_xport_channel_mapping();
+ //init some handler stuff
+ _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le);
+ _io_impl->recv_handler.set_converter(_rx_otw_type);
+ _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le);
+ _io_impl->send_handler.set_converter(_tx_otw_type);
+ _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet());
}
-void b100_impl::update_xport_channel_mapping(void){
- if (_io_impl.get() == NULL) return; //not inited yet
- //set all of the relevant properties on the handler
+void b100_impl::update_tick_rate(const double rate){
boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock();
- _io_impl->recv_handler.resize(_rx_subdev_spec.size());
- _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le);
- _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate());
- //FIXME assumes homogeneous rates across all dsp
- _io_impl->recv_handler.set_samp_rate(_rx_dsp_proxies[_rx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as<double>());
- for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){
- _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind(
- &b100_impl::io_impl::get_recv_buff, _io_impl.get(), chan, _1
- ));
- _io_impl->recv_handler.set_overflow_handler(chan, boost::bind(
- &b100_impl::handle_overrun, this, chan
+ _io_impl->recv_handler.set_tick_rate(rate);
+ boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock();
+ _io_impl->send_handler.set_tick_rate(rate);
+}
+
+void b100_impl::update_rx_samp_rate(const double rate){
+ boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock();
+ _io_impl->recv_handler.set_samp_rate(rate);
+}
+
+void b100_impl::update_tx_samp_rate(const double rate){
+ boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock();
+ _io_impl->send_handler.set_samp_rate(rate);
+}
+
+void b100_impl::update_rx_subdev_spec(const uhd::usrp::subdev_spec_t &spec){
+ boost::mutex::scoped_lock recv_lock = _io_impl->recv_handler.get_scoped_lock();
+ property_tree::path_type root = "/mboards/0/dboards";
+
+ //sanity checking
+ if (spec.size() == 0) throw uhd::value_error("rx subdev spec cant be empty");
+ if (spec.size() > _rx_dsps.size()) throw uhd::value_error("rx subdev spec too long");
+
+ //setup mux for this spec
+ for (size_t i = 0; i < spec.size(); i++){
+ //ASSUME that we dont swap the rx fe mux...
+ const std::string conn = _tree->access<std::string>(root / spec[i].db_name / "rx_frontends" / spec[i].sd_name / "connection").get();
+ _rx_dsps[i]->set_mux(conn);
+ }
+
+ //resize for the new occupancy
+ _io_impl->recv_handler.resize(spec.size());
+
+ //bind new callbacks for the handler
+ for (size_t i = 0; i < _io_impl->recv_handler.size(); i++){
+ _rx_dsps[i]->set_nsamps_per_packet(get_max_recv_samps_per_packet()); //seems to be a good place to set this
+ _io_impl->recv_handler.set_xport_chan_get_buff(i, boost::bind(
+ &b100_impl::io_impl::get_recv_buff, _io_impl.get(), i, _1
));
+ _io_impl->recv_handler.set_overflow_handler(i, boost::bind(&rx_dsp_core_200::handle_overflow, _rx_dsps[i]));
}
- _io_impl->recv_handler.set_converter(_recv_otw_type);
+}
- //set all of the relevant properties on the handler
+void b100_impl::update_tx_subdev_spec(const uhd::usrp::subdev_spec_t &spec){
boost::mutex::scoped_lock send_lock = _io_impl->send_handler.get_scoped_lock();
- _io_impl->send_handler.resize(_tx_subdev_spec.size());
- _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le);
- _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate());
- //FIXME assumes homogeneous rates across all dsp
- _io_impl->send_handler.set_samp_rate(_tx_dsp_proxies[_tx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as<double>());
- for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){
- _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind(
- &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_transport, _1
+ property_tree::path_type root = "/mboards/0/dboards";
+
+ //sanity checking
+ if (spec.size() != 1) throw uhd::value_error("tx subdev spec has to be size 1");
+
+ //set the mux for this spec
+ const std::string conn = _tree->access<std::string>(root / spec[0].db_name / "tx_frontends" / spec[0].sd_name / "connection").get();
+ _tx_fe->set_mux(conn);
+
+ //resize for the new occupancy
+ _io_impl->send_handler.resize(spec.size());
+
+ //bind new callbacks for the handler
+ for (size_t i = 0; i < _io_impl->send_handler.size(); i++){
+ _io_impl->recv_handler.set_xport_chan_get_buff(i, boost::bind(
+ &zero_copy_if::get_recv_buff, _data_transport, _1
));
}
- _io_impl->send_handler.set_converter(_send_otw_type);
- _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet());
}
/***********************************************************************
- * Data send + helper functions
+ * Async Data
+ **********************************************************************/
+bool b100_impl::recv_async_msg(uhd::async_metadata_t &md, double timeout){
+ return _fpga_ctrl->recv_async_msg(md, timeout);
+}
+
+/***********************************************************************
+ * Send Data
**********************************************************************/
size_t b100_impl::get_max_send_samps_per_packet(void) const {
static const size_t hdr_size = 0
@@ -149,7 +199,7 @@ size_t b100_impl::get_max_send_samps_per_packet(void) const {
- sizeof(vrt::if_packet_info_t().cid) //no class id ever used
;
static const size_t bpp = 2048 - hdr_size;
- return bpp / _send_otw_type.get_sample_size();
+ return bpp / _tx_otw_type.get_sample_size();
}
size_t b100_impl::send(
@@ -165,9 +215,8 @@ size_t b100_impl::send(
}
/***********************************************************************
- * Data recv + helper functions
+ * Receive Data
**********************************************************************/
-
size_t b100_impl::get_max_recv_samps_per_packet(void) const {
static const size_t hdr_size = 0
+ vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
@@ -175,7 +224,7 @@ size_t b100_impl::get_max_recv_samps_per_packet(void) const {
- sizeof(vrt::if_packet_info_t().cid) //no class id ever used
;
size_t bpp = 2048 - hdr_size; //limited by FPGA pkt buffer size
- return bpp/_recv_otw_type.get_sample_size();
+ return bpp/_rx_otw_type.get_sample_size();
}
size_t b100_impl::recv(
@@ -189,23 +238,3 @@ size_t b100_impl::recv(
recv_mode, timeout
);
}
-
-void b100_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, size_t index)
-{
- _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
- _iface->poke32(B100_REG_RX_CTRL_STREAM_CMD(index), dsp_type1::calc_stream_cmd_word(stream_cmd));
- _iface->poke32(B100_REG_RX_CTRL_TIME_SECS(index), boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
- _iface->poke32(B100_REG_RX_CTRL_TIME_TICKS(index), stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
-
- if (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) {
- while(_io_impl->data_transport->get_recv_buff().get() != NULL){
- /* NOP */
- }
- }
-}
-
-void b100_impl::handle_overrun(size_t index){
- if (_io_impl->continuous_streaming){
- this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS, index);
- }
-}