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author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-24 13:40:59 -0700 |
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committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-24 13:40:59 -0700 |
commit | b87c8b834abc6e0db80d06411b1c0983cd740c1d (patch) | |
tree | f594c834449042d8db1fc568b749cfec4a185a4c /host/lib/transport | |
parent | 290b85a9610eb416d21775b222e70b8772497b08 (diff) | |
download | uhd-b87c8b834abc6e0db80d06411b1c0983cd740c1d.tar.gz uhd-b87c8b834abc6e0db80d06411b1c0983cd740c1d.tar.bz2 uhd-b87c8b834abc6e0db80d06411b1c0983cd740c1d.zip |
x300: Updated FPGA->ADC Clock delays for all boards
- Delays changed after ADC config change and FPGA fixes
Diffstat (limited to 'host/lib/transport')
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