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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-04-24 13:01:37 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-04-24 13:01:37 -0700 |
| commit | 8e5fe11b6015c3456261d7b7b2ef6918fefa1ee8 (patch) | |
| tree | bf786bb47828939ae958b43094f16ca80cb1a88c /host/lib/transport/nirio_zero_copy.cpp | |
| parent | 4b4e493f976094115dad7809121a092e2ac31668 (diff) | |
| download | uhd-8e5fe11b6015c3456261d7b7b2ef6918fefa1ee8.tar.gz uhd-8e5fe11b6015c3456261d7b7b2ef6918fefa1ee8.tar.bz2 uhd-8e5fe11b6015c3456261d7b7b2ef6918fefa1ee8.zip | |
x300: Cleanup for PCIe flushing
Diffstat (limited to 'host/lib/transport/nirio_zero_copy.cpp')
| -rw-r--r-- | host/lib/transport/nirio_zero_copy.cpp | 54 |
1 files changed, 30 insertions, 24 deletions
diff --git a/host/lib/transport/nirio_zero_copy.cpp b/host/lib/transport/nirio_zero_copy.cpp index 87739b9c6..a739c01f1 100644 --- a/host/lib/transport/nirio_zero_copy.cpp +++ b/host/lib/transport/nirio_zero_copy.cpp @@ -292,34 +292,40 @@ private: static const uint32_t TIMEOUT_IN_MS = 100; uint32_t reg_data = 0xffffffff; + bool tx_busy = true, rx_busy = true; boost::posix_time::ptime start_time; boost::posix_time::time_duration elapsed; nirio_status status = NiRio_Status_Success; - start_time = boost::posix_time::microsec_clock::local_time(); - do { - boost::this_thread::sleep(boost::posix_time::microsec(50)); //Avoid flooding the bus - elapsed = boost::posix_time::microsec_clock::local_time() - start_time; - nirio_status_chain(_proxy().peek( - PCIE_TX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); - } while ( - nirio_status_not_fatal(status) && - (reg_data & DMA_STATUS_BUSY) && - elapsed.total_milliseconds() < TIMEOUT_IN_MS); - - start_time = boost::posix_time::microsec_clock::local_time(); - do { - boost::this_thread::sleep(boost::posix_time::microsec(50)); //Avoid flooding the bus - elapsed = boost::posix_time::microsec_clock::local_time() - start_time; - nirio_status_chain(_proxy().peek( - PCIE_RX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); - } while ( - nirio_status_not_fatal(status) && - (reg_data & DMA_STATUS_BUSY) && - elapsed.total_milliseconds() < TIMEOUT_IN_MS); - - nirio_status_to_exception(status, - "Could not create nirio_zero_copy transport because the FPGA is busy. Try re-downloading the LVBITX."); + nirio_status_chain(_proxy().peek( + PCIE_TX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); + tx_busy = (reg_data & DMA_STATUS_BUSY); + nirio_status_chain(_proxy().peek( + PCIE_RX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); + rx_busy = (reg_data & DMA_STATUS_BUSY); + + if (nirio_status_not_fatal(status) && !tx_busy && !rx_busy) { + start_time = boost::posix_time::microsec_clock::local_time(); + do { + boost::this_thread::sleep(boost::posix_time::microsec(50)); //Avoid flooding the bus + elapsed = boost::posix_time::microsec_clock::local_time() - start_time; + nirio_status_chain(_proxy().peek( + PCIE_TX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); + tx_busy = (reg_data & DMA_STATUS_BUSY); + nirio_status_chain(_proxy().peek( + PCIE_RX_DMA_REG(DMA_CTRL_STATUS_REG, _fifo_instance), reg_data), status); + rx_busy = (reg_data & DMA_STATUS_BUSY); + } while ( + nirio_status_not_fatal(status) && + (tx_busy || rx_busy) && + elapsed.total_milliseconds() < TIMEOUT_IN_MS); + + if (tx_busy || rx_busy) { + nirio_status_chain(NiRio_Status_FpgaBusy, status); + } + + nirio_status_to_exception(status, "Could not create nirio_zero_copy transport."); + } } //memory management -> buffers and fifos |