x300,nirio: Added support for NI-RIO 14.0

- Split niriok_proxy interfaces to support NI-RIO <=13.0 and >=14.0 kernel interfaces
- Fixed multi-session race conditions by synchronizing niriok_proxy access
- Fixed bug switching from NI LV-FPGA access to UHD access by changing how devices are hashed into a reservation table
- Fixed calculation of FRAC values for CBX and SBX LO tuning by rounding instead of truncating
- Fixed bug that was not setting two MSBs for band select configuration of CBX LO
- Submitting on behalf of Patrick Sisterhen, Matthew Crymble

1 files changed, 27 insertions, 1 deletions

diff --git a/host/lib/transport/nirio/lvbitx/process-lvbitx.py b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
index a3d88d0bb..ab9625608 100755
--- a/host/lib/transport/nirio/lvbitx/process-lvbitx.py
+++ b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
@@ -101,6 +101,31 @@ codegen_transform['control_list'] = control_list
 codegen_transform['indicator_list'] = indicator_list
 
 # Enumerate FIFOs
+
+# This function takes a SubType string as specified in an lvbitx file and finds the
+# corresponding nirio_scalar_type_t value.
+def map_SubType_to_ScalarType(SubType):
+    if SubType == 'I8':
+        ScalarType = 'RIO_SCALAR_TYPE_IB'
+    elif SubType == 'I16':
+        ScalarType = 'RIO_SCALAR_TYPE_IW'
+    elif SubType == 'I32':
+        ScalarType = 'RIO_SCALAR_TYPE_IL'
+    elif SubType == 'I64':
+        ScalarType = 'RIO_SCALAR_TYPE_IQ'
+    elif SubType == 'U8':
+        ScalarType = 'RIO_SCALAR_TYPE_UB'
+    elif SubType == 'U16':
+        ScalarType = 'RIO_SCALAR_TYPE_UW'
+    elif SubType == 'U32':
+        ScalarType = 'RIO_SCALAR_TYPE_UL'
+    elif SubType == 'U64':
+        ScalarType = 'RIO_SCALAR_TYPE_UQ'
+    else:
+        print 'ERROR: No corresponding nirio_scalar_type_t value for SubType ' + SubType + ' .'
+        sys.exit(1)
+    return ScalarType;
+
 nifpga_metadata = root.find('Project').find('CompilationResultsTree').find('CompilationResults').find('NiFpga')
 dma_channel_list = nifpga_metadata.find('DmaChannelAllocationList')
 reg_block_list = nifpga_metadata.find('RegisterBlockList')
@@ -133,8 +158,9 @@ for dma_channel in dma_channel_list:
     fifo_init_seq += direction + ', '
     fifo_init_seq += str.lower(base_addr) + ', '
     fifo_init_seq += dma_channel.find('NumberOfElements').text + ', '
-    fifo_init_seq += 'SCALAR_' + dma_channel.find('DataType').find('SubType').text + ', '
+    fifo_init_seq += map_SubType_to_ScalarType(dma_channel.find('DataType').find('SubType').text) + ', '
     fifo_init_seq += dma_channel.find('DataType').find('WordLength').text + ', '
+    fifo_init_seq += dma_channel.find('DataType').find('IntegerWordLength').text + ', '
     fifo_init_seq += bitstream_version
     fifo_init_seq += ')); //' + fifo_name