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| author | Martin Braun <martin.braun@ettus.com> | 2021-01-11 10:50:00 +0100 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-03-04 08:18:41 -0600 |
| commit | 01e65903c2e17ead3318b7ca7a3da7c8a906a3a0 (patch) | |
| tree | d9b5881cee2923bcf2e8719dad725443d05c0534 /host/lib/rfnoc | |
| parent | 107a49c0c236940da7d3bd0f57da4bc1e2a34cb4 (diff) | |
| download | uhd-01e65903c2e17ead3318b7ca7a3da7c8a906a3a0.tar.gz uhd-01e65903c2e17ead3318b7ca7a3da7c8a906a3a0.tar.bz2 uhd-01e65903c2e17ead3318b7ca7a3da7c8a906a3a0.zip | |
lib: Remove unused constants
The constants were either commented out, when their value is still
useful to the reader, or removed if not.
Diffstat (limited to 'host/lib/rfnoc')
| -rw-r--r-- | host/lib/rfnoc/dmafifo_block_control.cpp | 2 | ||||
| -rw-r--r-- | host/lib/rfnoc/mgmt_portal.cpp | 9 |
2 files changed, 5 insertions, 6 deletions
diff --git a/host/lib/rfnoc/dmafifo_block_control.cpp b/host/lib/rfnoc/dmafifo_block_control.cpp index c34746a28..efc8d27cb 100644 --- a/host/lib/rfnoc/dmafifo_block_control.cpp +++ b/host/lib/rfnoc/dmafifo_block_control.cpp @@ -15,8 +15,6 @@ using namespace uhd::rfnoc; namespace { -//! Default FIFO depth per channel: 32 MiB -constexpr uint32_t DEFAULT_SIZE = 32 * 1024 * 1024; constexpr uint64_t BYTES_PER_BIST = 8000000; constexpr double BIST_TIMEOUT = 0.5; // s //! Address space between FIFO controls diff --git a/host/lib/rfnoc/mgmt_portal.cpp b/host/lib/rfnoc/mgmt_portal.cpp index ea78aee48..42b8039c0 100644 --- a/host/lib/rfnoc/mgmt_portal.cpp +++ b/host/lib/rfnoc/mgmt_portal.cpp @@ -23,6 +23,7 @@ using namespace transport; constexpr bool ALLOW_DAISY_CHAINING = true; +// Unused values are left in as comments for reference. constexpr uint16_t REG_EPID_SELF = 0x00; // RW constexpr uint16_t REG_RESET_AND_FLUSH = 0x04; // W constexpr uint16_t REG_OSTRM_CTRL_STATUS = 0x08; // RW @@ -34,14 +35,14 @@ constexpr uint16_t REG_OSTRM_FC_HEADROOM = 0x1C; // W constexpr uint16_t REG_OSTRM_BUFF_CAP_BYTES_LO = 0x20; // R constexpr uint16_t REG_OSTRM_BUFF_CAP_BYTES_HI = 0x24; // R constexpr uint16_t REG_OSTRM_BUFF_CAP_PKTS = 0x28; // R -constexpr uint16_t REG_OSTRM_SEQ_ERR_CNT = 0x2C; // R -constexpr uint16_t REG_OSTRM_DATA_ERR_CNT = 0x30; // R -constexpr uint16_t REG_OSTRM_ROUTE_ERR_CNT = 0x34; // R +// constexpr uint16_t REG_OSTRM_SEQ_ERR_CNT = 0x2C; // R +// constexpr uint16_t REG_OSTRM_DATA_ERR_CNT = 0x30; // R +// constexpr uint16_t REG_OSTRM_ROUTE_ERR_CNT = 0x34; // R constexpr uint16_t REG_ISTRM_CTRL_STATUS = 0x38; // RW constexpr uint32_t RESET_AND_FLUSH_OSTRM = (1 << 0); constexpr uint32_t RESET_AND_FLUSH_ISTRM = (1 << 1); -constexpr uint32_t RESET_AND_FLUSH_CTRL = (1 << 2); +// constexpr uint32_t RESET_AND_FLUSH_CTRL = (1 << 2); constexpr uint32_t RESET_AND_FLUSH_ALL = 0x7; #ifdef UHD_BIG_ENDIAN |