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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2018-06-05 13:48:07 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-06-15 16:37:03 -0500 |
| commit | 67b5827faecd3dc3d9977dff7366b8ea2ab4c87a (patch) | |
| tree | 8d4d6b3645cd4b1aa72e26b4be4b5e81d5c45bfa /host/lib/include | |
| parent | f9101d7cc7552755d597982eeccecabe88b8a022 (diff) | |
| download | uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.tar.gz uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.tar.bz2 uhd-67b5827faecd3dc3d9977dff7366b8ea2ab4c87a.zip | |
ad9361: Add API to set 1R1T/2R2T timing modes
LVDS interface can support both timing modes 1R1T/2R2T
The API sets the required bit in catalina registers.
Diffstat (limited to 'host/lib/include')
| -rw-r--r-- | host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp b/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp index 411de6f81..07906fef2 100644 --- a/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp @@ -109,6 +109,9 @@ public: //! set which RX and TX chains/antennas are active virtual void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) = 0; + //! set which timing mode is used + virtual void set_timing_mode(const std::string &timing_mode) = 0; + //! tune the given frontend, return the exact value virtual double tune(const std::string &which, const double value) = 0; |