From 67b5827faecd3dc3d9977dff7366b8ea2ab4c87a Mon Sep 17 00:00:00 2001 From: Sugandha Gupta Date: Tue, 5 Jun 2018 13:48:07 -0700 Subject: ad9361: Add API to set 1R1T/2R2T timing modes LVDS interface can support both timing modes 1R1T/2R2T The API sets the required bit in catalina registers. --- host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'host/lib/include') diff --git a/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp b/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp index 411de6f81..07906fef2 100644 --- a/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp +++ b/host/lib/include/uhdlib/usrp/common/ad9361_ctrl.hpp @@ -109,6 +109,9 @@ public: //! set which RX and TX chains/antennas are active virtual void set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) = 0; + //! set which timing mode is used + virtual void set_timing_mode(const std::string &timing_mode) = 0; + //! tune the given frontend, return the exact value virtual double tune(const std::string &which, const double value) = 0; -- cgit v1.2.3