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| author | Ashish Chaudhari <ashish@ettus.com> | 2018-08-02 15:46:59 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish.chaudhari@ettus.com> | 2018-08-03 11:46:09 -0700 |
| commit | 22286176373246c53953ac6a1b2caf0dab879077 (patch) | |
| tree | 1dc83f26722838d4a82a397a77f30b55b8ea01ab /host/lib/include/uhdlib/usrp | |
| parent | 74fd6c9a81a066eedfd5b9f85160375d3aac552c (diff) | |
| download | uhd-22286176373246c53953ac6a1b2caf0dab879077.tar.gz uhd-22286176373246c53953ac6a1b2caf0dab879077.tar.bz2 uhd-22286176373246c53953ac6a1b2caf0dab879077.zip | |
rfnoc: dma_fifo: Added a more robust flush mechanism
- The flushing mechanism now looks similar to that in noc_shell
- Make use of new flush bit in FIFO control register
- Restrict using the clear bit only after flushing to ensure no
partial packets are introduced in the stream. (clear immediately
empties out FIFOs)
- Changes are backwards compatible with older FPGAs
Diffstat (limited to 'host/lib/include/uhdlib/usrp')
| -rw-r--r-- | host/lib/include/uhdlib/usrp/cores/dma_fifo_core_3000.hpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/include/uhdlib/usrp/cores/dma_fifo_core_3000.hpp b/host/lib/include/uhdlib/usrp/cores/dma_fifo_core_3000.hpp index 17c02c93a..1869191e3 100644 --- a/host/lib/include/uhdlib/usrp/cores/dma_fifo_core_3000.hpp +++ b/host/lib/include/uhdlib/usrp/cores/dma_fifo_core_3000.hpp @@ -34,7 +34,7 @@ public: /*! * Flush the DMA FIFO. Will clear all contents. */ - virtual void flush() = 0; + virtual bool flush(uint32_t timeout_ms = 2000) = 0; /*! * Resize and rebase the DMA FIFO. Will clear all contents. |