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| author | mattprost <matt.prost@ni.com> | 2020-07-28 13:29:38 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-08-11 16:07:16 -0500 |
| commit | fc3f91e0cfb77e295673ac04d310ded65863c119 (patch) | |
| tree | 83aec8d8f2d62bbb69a8c52873b085d11704e00a /host/lib/ic_reg_maps | |
| parent | de8b6fcd7137834defbb52242bc4cdec8adb167e (diff) | |
| download | uhd-fc3f91e0cfb77e295673ac04d310ded65863c119.tar.gz uhd-fc3f91e0cfb77e295673ac04d310ded65863c119.tar.bz2 uhd-fc3f91e0cfb77e295673ac04d310ded65863c119.zip | |
twinrx: update synthesizer register values for improved rf performance
Updated Register values for ADF5356:
R2) Expand Frac2 to a 28-bit value for ADF5356
R6) Use negative bleed current for improved spurious performance
R7) Set Fractional-N Lock Detect Precision to 12.0 ns because of bleed
currents
R8) Use magic number for reserved bits
R9) Fix VCO Band Division calculation for ADF5356
RD) Expand Frac2 to a 28-bit value for ADF5356
Signed-off-by: mattprost <matt.prost@ni.com>
Diffstat (limited to 'host/lib/ic_reg_maps')
| -rwxr-xr-x | host/lib/ic_reg_maps/gen_adf5356_regs.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/host/lib/ic_reg_maps/gen_adf5356_regs.py b/host/lib/ic_reg_maps/gen_adf5356_regs.py index 11662a67c..afa64220d 100755 --- a/host/lib/ic_reg_maps/gen_adf5356_regs.py +++ b/host/lib/ic_reg_maps/gen_adf5356_regs.py @@ -68,14 +68,14 @@ cp_bleed_current 6[13:20] 0 rf_divider_select 6[21:23] 0 div1, div2, div4, div8, div16, div32, div64 feedback_select 6[24] 0 divided, fundamental reg6_reserved2 6[25:28] 0xA -negative_bleed 6[29] 0 disabled, enabled +negative_bleed 6[29] 1 disabled, enabled gated_bleed 6[30] 0 disabled, enabled bleed_polarity 6[31] 0 negative, positive ######################################################################## ## address 7 ######################################################################## ld_mode 7[4] 0 frac_n, int_n -frac_n_ld_precision 7[5:6] 0 5ns, 6ns, 8ns, 12ns +frac_n_ld_precision 7[5:6] 0x3 5ns, 6ns, 8ns, 12ns loss_of_lock_mode 7[7] 0 disabled, enabled ld_cyc_count 7[8:9] 0 1024, 2048, 4096, 8192 reg7_reserved0 7[10:24] 0x0 @@ -86,7 +86,7 @@ reg7_reserved2 7[28:31] 0x0 ######################################################################## ## address 8 ######################################################################## -reg8_reserved0 8[4:31] 0x5559656 +reg8_reserved0 8[4:31] 0x102D042 ######################################################################## ## address 9 ######################################################################## |