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| author | David Raeman <david@synopticengineering.com> | 2022-03-08 02:50:06 +0000 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2022-04-01 13:30:05 -0700 |
| commit | 7a303df8e4a9c167691ffd242424be76559a712f (patch) | |
| tree | 5b7c5e0af6af20f188b84a920e7ed88ee81821b6 /host/lib/ic_reg_maps | |
| parent | acc731eeb70f948288b5ffcd64dc4b357356cc4e (diff) | |
| download | uhd-7a303df8e4a9c167691ffd242424be76559a712f.tar.gz uhd-7a303df8e4a9c167691ffd242424be76559a712f.tar.bz2 uhd-7a303df8e4a9c167691ffd242424be76559a712f.zip | |
n320: fix issue that occasionally prevents lo_locked upon first set_freq
For certain frequencies, the LMX2592 will sporadically fail to lock upon
the very first tune. When this happens, subsequent tunes (even to the same
frequency) do lock. This issue seems to be resolved by programming the FCAL
adjustment register fields (FCAL_LPFD_ADJ/FCAL_HPFD_ADJ) as described in
the LMX2592 datasheet. These fields adjust the FCAL calibration speed to
better accomodate PFD frequencies below 20MHz or above 100MHz.
This patch also fixes a few name typos in the register map that were
directly in the scope of this change.
Diffstat (limited to 'host/lib/ic_reg_maps')
| -rwxr-xr-x | host/lib/ic_reg_maps/gen_lmx2592_regs.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/ic_reg_maps/gen_lmx2592_regs.py b/host/lib/ic_reg_maps/gen_lmx2592_regs.py index 0d5f0be23..8a323928a 100755 --- a/host/lib/ic_reg_maps/gen_lmx2592_regs.py +++ b/host/lib/ic_reg_maps/gen_lmx2592_regs.py @@ -19,7 +19,7 @@ muxout_sel 0[2] 1 readback, lock_detect fcal_enable 0[3] 1 acal_enable 0[4] 1 fcal_lpfd_adj 0[5:6] 0 unused, 20mhz, 10mhz, 5mhz -fcal_hpfd_adf 0[7:8] 0 unused, 100mhz, 150mhz, 200mhz +fcal_hpfd_adj 0[7:8] 0 unused, 100mhz, 150mhz, 200mhz reg0_reserved0 0[9:12] 0x1 ld_enable 0[13] 1 reg0_reserved1 0[14:15] 0x0 @@ -78,7 +78,7 @@ reg12_reserved0 12[12:15] 0x7 ## address 13 ######################################################################## reg13_reserved0 13[0:7] 0x0 -pdf_ctl 13[8:9] 0 dual_pdf=0, single_pfd=3 +pfd_ctl 13[8:9] 0 dual_pfd=0, single_pfd=3 reg13_reserved1 13[10:13] 0x0 cp_enable 13[14] 1 reg13_reserved2 13[15] 0x0 |