uhd: Replacing Cheetah w/ Mako 0.4.2 (allows Python 3 compat)

1 files changed, 26 insertions, 17 deletions

diff --git a/host/lib/ic_reg_maps/gen_max2871_regs.py b/host/lib/ic_reg_maps/gen_max2871_regs.py
index 338a019d8..f591c1636 100644..100755
--- a/host/lib/ic_reg_maps/gen_max2871_regs.py
+++ b/host/lib/ic_reg_maps/gen_max2871_regs.py
@@ -28,8 +28,10 @@ REGS_TMPL="""\
 ## Write-only, default = 0x007D0000
 ########################################################################
 int_n_mode              0x00[31]        0       frac_n, int_n
-int_16_bit              0x00[15:30]     0x007D  ##Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode.
-frac_12_bit             0x00[3:14]      0       ##Frac divider: 0-4095
+## Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode.
+int_16_bit              0x00[15:30]     0x007D
+## Frac divider: 0-4095
+frac_12_bit             0x00[3:14]      0
 ########################################################################
 ## Address 0x01
 ## Charge pump control
@@ -38,8 +40,10 @@ frac_12_bit             0x00[3:14]      0       ##Frac divider: 0-4095
 res1                    0x01[31]        0
 cpl                     0x01[29:30]     1       disabled, enabled, res1, res2
 cpt                     0x01[27:28]     0       normal, reserved, force_source, force_sink
-phase_12_bit            0x01[15:26]     1       ##sets phase shift
-mod_12_bit              0x01[3:14]      0xFFF   ##VCO frac modulus
+## sets phase shift
+phase_12_bit            0x01[15:26]     1
+## VCO frac modulus
+mod_12_bit              0x01[3:14]      0xFFF
 ########################################################################
 ## Address 0x02
 ## Misc. control
@@ -50,10 +54,11 @@ low_noise_and_spur      0x02[29:30]     3       low_noise, reserved, low_spur_1,
 muxout                  0x02[26:28]     0x6     tri_state, high, low, rdiv, ndiv, ald, dld, sync, res8, res9, res10, res11, spi, res13, res14, res15
 reference_doubler       0x02[25]        0       disabled, enabled
 reference_divide_by_2   0x02[24]        0       disabled, enabled
-r_counter_10_bit        0x02[14:23]     1       ##R divider value, 1-1023
+## R divider value, 1-1023
+r_counter_10_bit        0x02[14:23]     1
 double_buffer           0x02[13]        0       disabled, enabled
-#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16)))
-charge_pump_current     0x02[9:12]      7       $current_setting_enums
+<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) %>\
+charge_pump_current     0x02[9:12]      7       ${current_setting_enums}
 ldf                     0x02[8]         0       frac_n, int_n
 ldp                     0x02[7]         0       10ns, 6ns
 pd_polarity             0x02[6]         1       negative, positive
@@ -65,14 +70,17 @@ counter_reset           0x02[3]         0       normal, reset
 ## VCO control
 ## Write-only, default = 0x0000000B
 ########################################################################
-vco                     0x03[26:31]     0       ##VCO subband selection, used when VAS disabledd
-shutdown_vas            0x03[25]        0       enabled, disabled ##VCO autoselect
+## VCO subband selection, used when VAS disabledd
+vco                     0x03[26:31]     0
+## VCO autoselect
+shutdown_vas            0x03[25]        0       enabled, disabled
 retune                  0x03[24]        1       disabled, enabled
 res3                    0x3[19:23]      0
 csm                     0x3[18]         0       disabled, enabled
 mutedel                 0x3[17]         0       disabled, enabled
 clock_div_mode          0x03[15:16]     0       clock_divider_off, fast_lock, phase, reserved
-clock_divider_12_bit    0x03[3:14]      1       ##clock divider, 1-4095
+## clock divider, 1-4095
+clock_divider_12_bit    0x03[3:14]      1
 ########################################################################
 ## Address 0x04
 ## RF output control
@@ -82,7 +90,8 @@ res4                    0x04[29:31]     0x3
 shutdown_ldo            0x04[28]        0       enabled, disabled
 shutdown_div            0x04[27]        0       enabled, disabled
 shutdown_ref            0x04[26]        0       enabled, disabled
-bs_msb                  0x04[24:25]     0       ##Band select MSBs
+## Band select MSBs
+bs_msb                  0x04[24:25]     0
 feedback_select         0x04[23]        1       divided, fundamental
 rf_divider_select       0x04[20:22]     0       div1, div2, div4, div8, div16, div32, div64, div128
 band_select_clock_div   0x04[12:19]     0
@@ -124,13 +133,13 @@ enum addr_t{
 boost::uint32_t get_reg(boost::uint8_t addr){
     boost::uint32_t reg = addr & 0x7;
     switch(addr){
-    #for $addr in range(5+1)
-    case $addr:
-        #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
-        reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
-        #end for
+    % for addr in range(5+1):
+    case ${addr}:
+        % for reg in filter(lambda r: r.get_addr() == addr, regs):
+        reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()};
+        % endfor
         break;
-    #end for
+    % endfor
     }
     return reg;
 }