aboutsummaryrefslogtreecommitdiffstats
path: root/host/lib/ic_reg_maps/gen_lmk04816_regs.py
diff options
context:
space:
mode:
authorLars Amsel <lars.amsel@ni.com>2021-06-04 08:27:50 +0200
committerAaron Rossetto <aaron.rossetto@ni.com>2021-06-10 12:01:53 -0500
commit2a575bf9b5a4942f60e979161764b9e942699e1e (patch)
tree2f0535625c30025559ebd7494a4b9e7122550a73 /host/lib/ic_reg_maps/gen_lmk04816_regs.py
parente17916220cc955fa219ae37f607626ba88c4afe3 (diff)
downloaduhd-2a575bf9b5a4942f60e979161764b9e942699e1e.tar.gz
uhd-2a575bf9b5a4942f60e979161764b9e942699e1e.tar.bz2
uhd-2a575bf9b5a4942f60e979161764b9e942699e1e.zip
uhd: Add support for the USRP X410
Co-authored-by: Lars Amsel <lars.amsel@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Virendra Kakade <virendra.kakade@ni.com> Co-authored-by: Lane Kolbly <lane.kolbly@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Andrew Lynch <andrew.lynch@ni.com> Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>
Diffstat (limited to 'host/lib/ic_reg_maps/gen_lmk04816_regs.py')
-rwxr-xr-xhost/lib/ic_reg_maps/gen_lmk04816_regs.py20
1 files changed, 19 insertions, 1 deletions
diff --git a/host/lib/ic_reg_maps/gen_lmk04816_regs.py b/host/lib/ic_reg_maps/gen_lmk04816_regs.py
index ccc82804f..1f6db9c5b 100755
--- a/host/lib/ic_reg_maps/gen_lmk04816_regs.py
+++ b/host/lib/ic_reg_maps/gen_lmk04816_regs.py
@@ -380,11 +380,29 @@ uint32_t get_reg(int addr){
}
"""
+PY_BODY_TMPL = """\
+def get_reg(self, addr):
+ reg = 0
+ % for addr in sorted(set(map(lambda r: r.get_addr(), regs))):
+ <% if_state = 'if' if loop.index == 0 else 'elif' %>
+ ${if_state} addr == ${addr}:
+ % for reg in filter(lambda r: r.get_addr() == addr, regs):
+ % if reg.get_enums():
+ reg |= (self.${reg.get_name()}.value & ${reg.get_mask()}) << ${reg.get_shift()}
+ % else:
+ reg |= (self.${reg.get_name()} & ${reg.get_mask()}) << ${reg.get_shift()}
+ % endif
+ % endfor
+ % endfor
+ return reg
+
+"""
+
if __name__ == '__main__':
import common; common.generate(
name='lmk04816_regs',
regs_tmpl=REGS_TMPL,
body_tmpl=BODY_TMPL,
+ py_body_tmpl=PY_BODY_TMPL,
file=__file__,
)
-