rfnoc: Add DMA FIFO block controller

5 files changed, 510 insertions, 0 deletions

diff --git a/host/include/uhd/rfnoc/CMakeLists.txt b/host/include/uhd/rfnoc/CMakeLists.txt
index 20c8cc38a..9abacbeaa 100644
--- a/host/include/uhd/rfnoc/CMakeLists.txt
+++ b/host/include/uhd/rfnoc/CMakeLists.txt
@@ -33,6 +33,7 @@ UHD_INSTALL(FILES
     block_control.hpp
     ddc_block_control.hpp
     duc_block_control.hpp
+    dmafifo_block_control.hpp
     null_block_control.hpp
     radio_control.hpp
 
diff --git a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml
new file mode 100644
index 000000000..ddb7eed28
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_2x64.yml
@@ -0,0 +1,82 @@
+schema: rfnoc_modtool_args
+module_name: axi_ram_fifo
+version: 1.0
+rfnoc_version: 1.0
+chdr_width: 64
+noc_id: 0xF1F00000
+
+clocks:
+  - name: rfnoc_chdr
+    freq: "[]"
+  - name: rfnoc_ctrl
+    freq: "[]"
+
+control:
+  sw_iface: nocscript
+  fpga_iface: ctrlport
+  interface_direction: master_slave
+  fifo_depth: 32
+  clk_domain: rfnoc_ctrl
+  ctrlport:
+    byte_mode: True
+    timed: False
+    has_status: False
+
+# The parameters section lists parameters that get added to the generated
+# Verilog for the module instantiation. Any parameter listed here may be set to
+# different value in the image builder YAML file.
+parameters:
+  NUM_PORTS: 2
+  MEM_DATA_W: 64
+  MEM_ADDR_W: 30
+  FIFO_ADDR_BASE: "{30'h02000000, 30'h00000000}"
+  FIFO_ADDR_MASK: "{30'h01FFFFFF, 30'h01FFFFFF}"
+  MEM_CLK_RATE: "300e6"
+
+data:
+  fpga_iface: axis_chdr
+  clk_domain: rfnoc_chdr
+  mtu: 1024
+  inputs:
+    port0:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port1:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+  outputs:
+    port0:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port1:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+
+io_ports:
+  axi_ram:
+    type: axi4_mm_2x64_4g
+    drive: slave
+
+registers:
+
+properties:
diff --git a/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml
new file mode 100644
index 000000000..8fed9d6a2
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/axi_ram_fifo_4x64.yml
@@ -0,0 +1,114 @@
+schema: rfnoc_modtool_args
+module_name: axi_ram_fifo
+version: 1.0
+rfnoc_version: 1.0
+chdr_width: 64
+noc_id: 0xF1F00000
+
+clocks:
+  - name: rfnoc_chdr
+    freq: "[]"
+  - name: rfnoc_ctrl
+    freq: "[]"
+
+control:
+  sw_iface: nocscript
+  fpga_iface: ctrlport
+  interface_direction: master_slave
+  fifo_depth: 32
+  clk_domain: rfnoc_ctrl
+  ctrlport:
+    byte_mode: True
+    timed: False
+    has_status: False
+
+# The parameters section lists parameters that get added to the generated
+# Verilog for the module instantiation. Any parameter listed here may be set to
+# different value in the image builder YAML file.
+parameters:
+  NUM_PORTS: 4
+  MEM_DATA_W: 64
+  MEM_ADDR_W: 32
+  FIFO_ADDR_BASE: "{32'hC0000000, 32'h80000000, 32'h40000000, 32'h00000000}"
+  FIFO_ADDR_MASK: "{32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF, 32'h3FFFFFFF}"
+  MEM_CLK_RATE: "300e6"
+
+data:
+  fpga_iface: axis_chdr
+  clk_domain: rfnoc_chdr
+  mtu: 1024
+  inputs:
+    port0:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port1:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port2:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port3:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+  outputs:
+    port0:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port1:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port2:
+      index: 0
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+    port3:
+      index: 1
+      item_width: 32
+      nipc: 2
+      context_fifo_depth: 1
+      payload_fifo_depth: 1
+      format: int32
+      mdata_sig: ~
+
+io_ports:
+  axi_ram:
+    type: axi4_mm_4x64_4g
+    drive: slave
+
+registers:
+
+properties:
diff --git a/host/include/uhd/rfnoc/core/io_signatures.yml b/host/include/uhd/rfnoc/core/io_signatures.yml
index ba7721e3e..57e1b11c9 100644
--- a/host/include/uhd/rfnoc/core/io_signatures.yml
+++ b/host/include/uhd/rfnoc/core/io_signatures.yml
@@ -77,3 +77,291 @@ x300_radio:
   - name: radio_tx_running
     type: to-master
     width: 2
+
+# A 2-port AXI4 memory-mapped interface with 64-bit data, and 2 GiB address
+# space (32-bit).
+axi4_mm_2x64_4g:
+  type: master-slave
+  ports:
+  - name: mem_clk
+    type: from-master
+    width: 1
+  - name: mem_rst
+    type: from-master
+    width: 1
+  - name: m_axi_awid
+    type: to-master
+    width: 2
+  - name: m_axi_awaddr
+    type: to-master
+    width: 64
+  - name: m_axi_awlen
+    type: to-master
+    width: 16
+  - name: m_axi_awsize
+    type: to-master
+    width: 6
+  - name: m_axi_awburst
+    type: to-master
+    width: 4
+  - name: m_axi_awlock
+    type: to-master
+    width: 2
+  - name: m_axi_awcache
+    type: to-master
+    width: 8
+  - name: m_axi_awprot
+    type: to-master
+    width: 6
+  - name: m_axi_awqos
+    type: to-master
+    width: 8
+  - name: m_axi_awregion
+    type: to-master
+    width: 8
+  - name: m_axi_awuser
+    type: to-master
+    width: 2
+  - name: m_axi_awvalid
+    type: to-master
+    width: 2
+  - name: m_axi_awready
+    type: from-master
+    width: 2
+  - name: m_axi_wdata
+    type: to-master
+    width: 128
+  - name: m_axi_wstrb
+    type: to-master
+    width: 16
+  - name: m_axi_wlast
+    type: to-master
+    width: 2
+  - name: m_axi_wuser
+    type: to-master
+    width: 2
+  - name: m_axi_wvalid
+    type: to-master
+    width: 2
+  - name: m_axi_wready
+    type: from-master
+    width: 2
+  - name: m_axi_bid
+    type: from-master
+    width: 2
+  - name: m_axi_bresp
+    type: from-master
+    width: 4
+  - name: m_axi_buser
+    type: from-master
+    width: 2
+  - name: m_axi_bvalid
+    type: from-master
+    width: 2
+  - name: m_axi_bready
+    type: to-master
+    width: 2
+  - name: m_axi_arid
+    type: to-master
+    width: 2
+  - name: m_axi_araddr
+    type: to-master
+    width: 64
+  - name: m_axi_arlen
+    type: to-master
+    width: 16
+  - name: m_axi_arsize
+    type: to-master
+    width: 6
+  - name: m_axi_arburst
+    type: to-master
+    width: 4
+  - name: m_axi_arlock
+    type: to-master
+    width: 2
+  - name: m_axi_arcache
+    type: to-master
+    width: 8
+  - name: m_axi_arprot
+    type: to-master
+    width: 6
+  - name: m_axi_arqos
+    type: to-master
+    width: 8
+  - name: m_axi_arregion
+    type: to-master
+    width: 8
+  - name: m_axi_aruser
+    type: to-master
+    width: 2
+  - name: m_axi_arvalid
+    type: to-master
+    width: 2
+  - name: m_axi_arready
+    type: from-master
+    width: 2
+  - name: m_axi_rid
+    type: from-master
+    width: 2
+  - name: m_axi_rdata
+    type: from-master
+    width: 128
+  - name: m_axi_rresp
+    type: from-master
+    width: 4
+  - name: m_axi_rlast
+    type: from-master
+    width: 2
+  - name: m_axi_ruser
+    type: from-master
+    width: 2
+  - name: m_axi_rvalid
+    type: from-master
+    width: 2
+  - name: m_axi_rready
+    type: to-master
+    width: 2
+
+# A 4-port AXI4 memory-mapped interface with 64-bit data, and 4 GiB address
+# space (32-bit).
+axi4_mm_4x64_4g:
+  type: master-slave
+  ports:
+  - name: mem_clk
+    type: from-master
+    width: 1
+  - name: mem_rst
+    type: from-master
+    width: 1
+  - name: m_axi_awid
+    type: to-master
+    width: 4
+  - name: m_axi_awaddr
+    type: to-master
+    width: 128
+  - name: m_axi_awlen
+    type: to-master
+    width: 32
+  - name: m_axi_awsize
+    type: to-master
+    width: 12
+  - name: m_axi_awburst
+    type: to-master
+    width: 8
+  - name: m_axi_awlock
+    type: to-master
+    width: 4
+  - name: m_axi_awcache
+    type: to-master
+    width: 16
+  - name: m_axi_awprot
+    type: to-master
+    width: 12
+  - name: m_axi_awqos
+    type: to-master
+    width: 16
+  - name: m_axi_awregion
+    type: to-master
+    width: 16
+  - name: m_axi_awuser
+    type: to-master
+    width: 4
+  - name: m_axi_awvalid
+    type: to-master
+    width: 4
+  - name: m_axi_awready
+    type: from-master
+    width: 4
+  - name: m_axi_wdata
+    type: to-master
+    width: 256
+  - name: m_axi_wstrb
+    type: to-master
+    width: 32
+  - name: m_axi_wlast
+    type: to-master
+    width: 4
+  - name: m_axi_wuser
+    type: to-master
+    width: 4
+  - name: m_axi_wvalid
+    type: to-master
+    width: 4
+  - name: m_axi_wready
+    type: from-master
+    width: 4
+  - name: m_axi_bid
+    type: from-master
+    width: 4
+  - name: m_axi_bresp
+    type: from-master
+    width: 8
+  - name: m_axi_buser
+    type: from-master
+    width: 4
+  - name: m_axi_bvalid
+    type: from-master
+    width: 4
+  - name: m_axi_bready
+    type: to-master
+    width: 4
+  - name: m_axi_arid
+    type: to-master
+    width: 4
+  - name: m_axi_araddr
+    type: to-master
+    width: 128
+  - name: m_axi_arlen
+    type: to-master
+    width: 32
+  - name: m_axi_arsize
+    type: to-master
+    width: 12
+  - name: m_axi_arburst
+    type: to-master
+    width: 8
+  - name: m_axi_arlock
+    type: to-master
+    width: 4
+  - name: m_axi_arcache
+    type: to-master
+    width: 16
+  - name: m_axi_arprot
+    type: to-master
+    width: 12
+  - name: m_axi_arqos
+    type: to-master
+    width: 16
+  - name: m_axi_arregion
+    type: to-master
+    width: 16
+  - name: m_axi_aruser
+    type: to-master
+    width: 4
+  - name: m_axi_arvalid
+    type: to-master
+    width: 4
+  - name: m_axi_arready
+    type: from-master
+    width: 4
+  - name: m_axi_rid
+    type: from-master
+    width: 4
+  - name: m_axi_rdata
+    type: from-master
+    width: 256
+  - name: m_axi_rresp
+    type: from-master
+    width: 8
+  - name: m_axi_rlast
+    type: from-master
+    width: 4
+  - name: m_axi_ruser
+    type: from-master
+    width: 4
+  - name: m_axi_rvalid
+    type: from-master
+    width: 4
+  - name: m_axi_rready
+    type: to-master
+    width: 4
diff --git a/host/include/uhd/rfnoc/dmafifo_block_control.hpp b/host/include/uhd/rfnoc/dmafifo_block_control.hpp
new file mode 100644
index 000000000..ea15efef2
--- /dev/null
+++ b/host/include/uhd/rfnoc/dmafifo_block_control.hpp
@@ -0,0 +1,25 @@
+//
+// Copyright 2019 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+
+#ifndef INCLUDED_LIBUHD_DMAFIFO_BLOCK_CONTROL_HPP
+#define INCLUDED_LIBUHD_DMAFIFO_BLOCK_CONTROL_HPP
+
+#include <uhd/config.hpp>
+#include <uhd/rfnoc/noc_block_base.hpp>
+
+namespace uhd { namespace rfnoc {
+
+/*! DMA FIFO Block Control Class
+ */
+class UHD_API dmafifo_block_control : public noc_block_base
+{
+public:
+    RFNOC_DECLARE_BLOCK(dmafifo_block_control)
+};
+
+}} // namespace uhd::rfnoc
+
+#endif /* INCLUDED_LIBUHD_DMAFIFO_BLOCK_CONTROL_HPP */