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| author | steviez <steve.czabaniuk@ni.com> | 2020-07-31 12:08:19 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-31 14:32:54 -0500 |
| commit | ae2b9bf7aeea6f8f98f6dacffdfc018d87107927 (patch) | |
| tree | fa347454688a166df980e3d152133a2af07c2308 /host/examples/tx_samples_from_file.cpp | |
| parent | b5575603e1dd06efa2d0309b7efb0b92a7519316 (diff) | |
| download | uhd-ae2b9bf7aeea6f8f98f6dacffdfc018d87107927.tar.gz uhd-ae2b9bf7aeea6f8f98f6dacffdfc018d87107927.tar.bz2 uhd-ae2b9bf7aeea6f8f98f6dacffdfc018d87107927.zip | |
fpga: n320: Add BIST (AA) image files
This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.
This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.
Diffstat (limited to 'host/examples/tx_samples_from_file.cpp')
0 files changed, 0 insertions, 0 deletions