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authorSugandha Gupta <sugandha.gupta@ettus.com>2019-10-15 11:52:46 -0700
committerMartin Braun <martin.braun@ettus.com>2019-11-26 12:21:32 -0800
commita801d6b046743140e9a50c7788dd17dd71f5540a (patch)
tree58d164e1b4cb2a8d871ca532287699f3912ae3d8 /host/examples/rfnoc-example/fpga/CMakeLists.txt
parent2a7e69d862f661075b98bab19e58d958c28a9af8 (diff)
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examples: Add example out-of-tree module for RFNoC modules
This subdirectory is its own, self-contained project. It is supposed to work against the UHD version it is shipped with. Co-Authored-By: Martin Braun <martin.braun@ettus.com> Co-Authored-By: Wade Fife <wade.fife@ni.com>
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+#
+# Copyright 2019 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+
+# List Makefile.srcs here (which needs to point to the individual blocks!) as
+# well as any non-block specific HDL files that should get installed alongside
+# the rest of the FPGA/Verilog/VHDL/HDL files. Only list files that are required
+# for synthesis, testbench-specific files do not get installed and thus do not
+# have to be listed (it won't hurt, it will just clutter your share/ directory).
+# Don't list the files in the block subdirectories, though, they will get added
+# below.
+install(FILES
+ Makefile.srcs
+ DESTINATION ${PROJECT_DATA_DIR}/fpga
+ COMPONENT fpga
+)
+
+# Now call add_subdirectory() for every block subdir
+add_subdirectory(rfnoc_block_gain)
+