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author | Martin Braun <martin.braun@ettus.com> | 2018-10-30 17:05:17 -0700 |
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committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-11-07 17:00:10 -0800 |
commit | 2373f3267a5aa975064e30060b2dcf909c462a93 (patch) | |
tree | 473f6c012b33f79645949c2977467b3f361771b1 /host/docs/usrp_x3x0.dox | |
parent | 2493f31820024ed962095dcd36223c6a21224be4 (diff) | |
download | uhd-2373f3267a5aa975064e30060b2dcf909c462a93.tar.gz uhd-2373f3267a5aa975064e30060b2dcf909c462a93.tar.bz2 uhd-2373f3267a5aa975064e30060b2dcf909c462a93.zip |
x300: Remove 120 MHz option
None of our FPGA images support a 120 MHz master clock rate, so the UHD
code should match that.
Diffstat (limited to 'host/docs/usrp_x3x0.dox')
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