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authorMartin Braun <martin.braun@ettus.com>2018-10-30 17:05:17 -0700
committerBrent Stapleton <bstapleton@g.hmc.edu>2018-11-07 17:00:10 -0800
commit2373f3267a5aa975064e30060b2dcf909c462a93 (patch)
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parent2493f31820024ed962095dcd36223c6a21224be4 (diff)
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x300: Remove 120 MHz option
None of our FPGA images support a 120 MHz master clock rate, so the UHD code should match that.
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