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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-11-06 14:21:39 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-11-13 01:16:18 +0100 |
| commit | 265db795c26cf9609f8f1288484f85788cbf7b3d (patch) | |
| tree | 682c9a4b6ebb204a5ac896f392a01836b86c8815 /host/docs/usrp_e3x0.dox | |
| parent | bda6bcb2301281304981380cb804babcc681641a (diff) | |
| download | uhd-265db795c26cf9609f8f1288484f85788cbf7b3d.tar.gz uhd-265db795c26cf9609f8f1288484f85788cbf7b3d.tar.bz2 uhd-265db795c26cf9609f8f1288484f85788cbf7b3d.zip | |
x300: Cleaned up DAC ctrl and clock init logic
- DAC: Squashed configuration into 2 main operations: reset and reset_and_resync
- DAC: Put in sleep mode during configuration
- DAC: Synchronize only if streaming to more than one DAC
- DAC: Use falling edge sync mode
- DAC: Fixed power up/down settings
- DAC: Frontend sync failure is fatal
- Clocks: Refactored clock source change logic
- Clocks: Cleaned up init and lock-check sequence
Diffstat (limited to 'host/docs/usrp_e3x0.dox')
0 files changed, 0 insertions, 0 deletions