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| author | Martin Braun <martin.braun@ettus.com> | 2017-01-24 12:02:47 +0000 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-01-24 12:02:47 +0000 |
| commit | e4efbd007e4960ee6384e9d0a7eb013d865f216e (patch) | |
| tree | d625a496ac7699f7160717beff31ecd512c31551 /host/docs/usrp_e3x0.dox | |
| parent | cc4c2cbe374e37ac537aee846ef21cf7c52a34c9 (diff) | |
| download | uhd-e4efbd007e4960ee6384e9d0a7eb013d865f216e.tar.gz uhd-e4efbd007e4960ee6384e9d0a7eb013d865f216e.tar.bz2 uhd-e4efbd007e4960ee6384e9d0a7eb013d865f216e.zip | |
docs: Removed ambiguous statement on timed commands for E310
Diffstat (limited to 'host/docs/usrp_e3x0.dox')
| -rw-r--r-- | host/docs/usrp_e3x0.dox | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox index 470f6a26b..929b9f635 100644 --- a/host/docs/usrp_e3x0.dox +++ b/host/docs/usrp_e3x0.dox @@ -18,7 +18,6 @@ - FPGA Capabilities: - 2 RX DDC chains in FPGA - 2 TX DUC chain in FPGA - - Timed commands in FPGA - Timed sampling in FPGA - 16-bit fixed point sample mode (sc16) |