From e4efbd007e4960ee6384e9d0a7eb013d865f216e Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Tue, 24 Jan 2017 12:02:47 +0000
Subject: docs: Removed ambiguous statement on timed commands for E310

---
 host/docs/usrp_e3x0.dox | 1 -
 1 file changed, 1 deletion(-)

(limited to 'host/docs/usrp_e3x0.dox')

diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox
index 470f6a26b..929b9f635 100644
--- a/host/docs/usrp_e3x0.dox
+++ b/host/docs/usrp_e3x0.dox
@@ -18,7 +18,6 @@
 - FPGA Capabilities:
         - 2 RX DDC chains in FPGA
         - 2 TX DUC chain in FPGA
-	- Timed commands in FPGA
 	- Timed sampling in FPGA
 	- 16-bit fixed point sample mode (sc16)
 
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