aboutsummaryrefslogtreecommitdiffstats
path: root/host/docs/usrp_b200.dox
diff options
context:
space:
mode:
authorMartin Braun <martin.braun@ettus.com>2014-03-23 15:11:26 +0100
committerMartin Braun <martin.braun@ettus.com>2014-04-09 17:25:09 +0200
commita74919c2a89a6b1ae40b526c4ceadf1108bfd186 (patch)
tree79cb43c5d7ed3caa1fe8b695001267f0cc8286bf /host/docs/usrp_b200.dox
parent47bf17b50a305228cfd07ff6fbaff3ac4a30e811 (diff)
downloaduhd-a74919c2a89a6b1ae40b526c4ceadf1108bfd186.tar.gz
uhd-a74919c2a89a6b1ae40b526c4ceadf1108bfd186.tar.bz2
uhd-a74919c2a89a6b1ae40b526c4ceadf1108bfd186.zip
docs: Moved manual to Doxygen
Diffstat (limited to 'host/docs/usrp_b200.dox')
-rw-r--r--host/docs/usrp_b200.dox69
1 files changed, 69 insertions, 0 deletions
diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox
new file mode 100644
index 000000000..77b20ed01
--- /dev/null
+++ b/host/docs/usrp_b200.dox
@@ -0,0 +1,69 @@
+/*! \page page_usrp_b200 USRP-B2x0 Series Device Manual
+
+\tableofcontents
+
+\section b200_features Comparative features list - B200
+
+- Hardware Capabilities:
+ - Integrated RF frontend (70 MHz - 6 GHz)
+ - External PPS reference input
+ - External 10 MHz reference input
+ - Configurable clock rate
+ - Internal GPSDO option
+ - B210 Only:
+ - MICTOR Debug Connector
+ - JTAG Connector
+- FPGA Capabilities:
+ - Timed commands in FPGA
+ - Timed sampling in FPGA
+
+\section b200_imgs Specify a Non-standard Image
+
+UHD software will automatically select the USRP B2X0 images from the
+installed images package. The image selection can be overridden with the
+`fpga` and `fw` device address parameters.
+
+Example device address string representations to specify non-standard
+images:
+
+ fpga=usrp_b200_fpga.bin
+
+ -- OR --
+
+ fw=usrp_b200_fw.hex
+
+\section b200_mcr Changing the Master Clock Rate
+
+The master clock rate feeds the RF frontends and the DSP chains. Users
+may select non-default clock rates to acheive integer decimations or
+interpolations in the DSP chains. The default master clock rate defaults
+to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz.
+
+The user can set the master clock rate through the usrp API call
+uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the
+device arguments, which many applications take: :
+
+ uhd_usrp_probe --args="master_clock_rate=52e6"
+
+\section b200_fe RF Frontend Notes
+
+The B200 features an integrated RF frontend.
+
+\subsection b200_fe_tuning Frontend tuning
+
+The RF frontend has individually tunable receive and transmit chains. On
+the B200, there is one transmit and one receive RF frontend. On the
+B210, both transmit and receive can be used in a MIMO configuration. For
+the MIMO case, both receive frontends share the RX LO, and both transmit
+frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.
+
+\subsection b200_fe_gain Frontend gain
+
+All frontends have individual analog gain controls. The receive
+frontends have 73 dB of available gain; and the transmit frontends have
+89.5 dB of available gain. Gain settings are application specific, but
+it is recommended that users consider using at least half of the
+available gain to get reasonable dynamic range.
+
+*/
+// vim:ft=doxygen: