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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-03-12 10:24:33 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-03-12 10:24:33 -0700 |
| commit | 5682321efa26bb97f5d0c37d8e9921fc11a9b923 (patch) | |
| tree | 224e88034bb00bb91ab5c70f9160a0ac30e1c583 /host/docs/uhd.dox | |
| parent | 230cf5d76ac2417c36713e82bcd0fbe7986b7847 (diff) | |
| download | uhd-5682321efa26bb97f5d0c37d8e9921fc11a9b923.tar.gz uhd-5682321efa26bb97f5d0c37d8e9921fc11a9b923.tar.bz2 uhd-5682321efa26bb97f5d0c37d8e9921fc11a9b923.zip | |
x300: Timing changes for the new DAC data interface
- Switched DAC to DCI delay bypass mode because we
shift the DCI in the FPGA now
- Changed LMK control to add 900ps delay to DAC clocks
to be consistent with the radio_clk delay. The timing
analyzer is expecting the two clocks to have a 0 deg
phase diff.
Diffstat (limited to 'host/docs/uhd.dox')
0 files changed, 0 insertions, 0 deletions