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| author | Tom Tsou <tom.tsou@ettus.com> | 2017-07-07 15:32:20 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-07-25 10:15:37 -0700 |
| commit | 0e9f204029e5eac51d94f16ceb19f003e3faf7e8 (patch) | |
| tree | ad71a66f4aa84fc17e965d8682741584f64aa18d /host/docs/rd_testing.dox | |
| parent | 8223a289727bbda353bd7129512daf00d46d898c (diff) | |
| download | uhd-0e9f204029e5eac51d94f16ceb19f003e3faf7e8.tar.gz uhd-0e9f204029e5eac51d94f16ceb19f003e3faf7e8.tar.bz2 uhd-0e9f204029e5eac51d94f16ceb19f003e3faf7e8.zip | |
convert: Add SSE implementation for sc12
Implementation uses SSSE3 intructions to perform 12-bit
sample pack/unpack operations to/from standard 16 and 32
bit host values. Input/output shuffle orderings for a
single 128-bit SSE register with 16-bit integers shown
below.
16-bit interleaved I/Q
---------------------------------------
| Q3 | I3 | Q2 | I2 | Q1 | I1 | Q0 | I0 | Input
---------------------------------------
| 127 0 |
12-bit packed I/Q byteswapped
-----------------------
| I0 | Q0 | I1 | 0
|-----------------------|
| I1 | Q1 | I2 | Q2 | Output
|-----------------------|
| Q2 | I3 | Q3 |
|-----------------------|
| Unused | 3
-----------------------
31 0
Fixes: #1740, #966
Related: #1739
Diffstat (limited to 'host/docs/rd_testing.dox')
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