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| author | Jonathon Pendlum <jonathon.pendlum@ettus.com> | 2015-04-24 15:57:28 -0700 |
|---|---|---|
| committer | Jonathon Pendlum <jonathon.pendlum@ettus.com> | 2015-04-24 15:57:28 -0700 |
| commit | 65428849a51a9c6d74dff1f935b57d1ba904e5a6 (patch) | |
| tree | 830a413ebc4b123a44727dbd00d976acafc0d35e /host/docs/Doxyfile.in | |
| parent | 64990acea741768becafb3e9dee171274f23f9d9 (diff) | |
| download | uhd-65428849a51a9c6d74dff1f935b57d1ba904e5a6.tar.gz uhd-65428849a51a9c6d74dff1f935b57d1ba904e5a6.tar.bz2 uhd-65428849a51a9c6d74dff1f935b57d1ba904e5a6.zip | |
e300: Added minimum master clock rate restriction
- Master clock rate cannot be less than 10 MHz, which is the
MMCM's minimum operating frequency in the FPGA's capture
interface.
Diffstat (limited to 'host/docs/Doxyfile.in')
0 files changed, 0 insertions, 0 deletions