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authorJonathon Pendlum <jonathon.pendlum@ettus.com>2015-04-24 15:57:28 -0700
committerJonathon Pendlum <jonathon.pendlum@ettus.com>2015-04-24 15:57:28 -0700
commit65428849a51a9c6d74dff1f935b57d1ba904e5a6 (patch)
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parent64990acea741768becafb3e9dee171274f23f9d9 (diff)
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e300: Added minimum master clock rate restriction
- Master clock rate cannot be less than 10 MHz, which is the MMCM's minimum operating frequency in the FPGA's capture interface.
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