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| author | Wade Fife <wade.fife@ettus.com> | 2021-12-15 17:16:32 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-12-15 17:16:32 -0600 |
| commit | 610488690a5f7bf1dd828aa6b9a70dd0874ca87f (patch) | |
| tree | 275e314ae06d91e49ed05c9ff8523281559ef3e6 /fpga | |
| parent | 520fc00e2b427f6682bf8e47ccbad6e5e068a0da (diff) | |
| download | uhd-610488690a5f7bf1dd828aa6b9a70dd0874ca87f.tar.gz uhd-610488690a5f7bf1dd828aa6b9a70dd0874ca87f.tar.bz2 uhd-610488690a5f7bf1dd828aa6b9a70dd0874ca87f.zip | |
fpga: x300: Fix time register readback
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/x300/bus_int.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v index 4ca05c5fe..90f840a4c 100644 --- a/fpga/usrp3/top/x300/bus_int.v +++ b/fpga/usrp3/top/x300/bus_int.v @@ -439,12 +439,12 @@ module bus_int #( RB_FP_GPIO_SRC: rb_data = fp_gpio_src; SR_BASE_TIME: begin rb_data = radio_time[31:0]; - radio_time_hi_ld = 1'b1; + radio_time_hi_ld = rb_rd_stb; end SR_BASE_TIME + 'h04: rb_data = radio_time_hi; SR_BASE_TIME + 'h14: begin rb_data = radio_time_last_pps[31:0]; - radio_time_last_pps_hi_ld = 1'b1; + radio_time_last_pps_hi_ld = rb_rd_stb; end SR_BASE_TIME + 'h18: rb_data = radio_time_last_pps_hi; SR_BASE_TIME + 'h1C: rb_data = period_ns_q32_tb[31:0]; |