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| author | Josh Blum <josh@joshknows.com> | 2011-03-17 13:47:06 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-03-17 13:47:06 -0700 |
| commit | 2d906e6708469cbac63fac6dfd95391f0ecc1aec (patch) | |
| tree | d08fb4ecd184a5f09d6e2d4d37af933c6cd1edcf /fpga | |
| parent | 31953ec55d038d75cfe9307bd38abdc953904b07 (diff) | |
| parent | 74979af6a089c67ac6579cb08040aec305032018 (diff) | |
| download | uhd-2d906e6708469cbac63fac6dfd95391f0ecc1aec.tar.gz uhd-2d906e6708469cbac63fac6dfd95391f0ecc1aec.tar.bz2 uhd-2d906e6708469cbac63fac6dfd95391f0ecc1aec.zip | |
Merge branch 'fpga_master' into next
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp2/fifo/packet_verifier32.v | 23 | ||||
| -rw-r--r-- | fpga/usrp2/top/u1e/u1e_core.v | 1 |
2 files changed, 8 insertions, 16 deletions
diff --git a/fpga/usrp2/fifo/packet_verifier32.v b/fpga/usrp2/fifo/packet_verifier32.v index 06a13d242..ec08e657d 100644 --- a/fpga/usrp2/fifo/packet_verifier32.v +++ b/fpga/usrp2/fifo/packet_verifier32.v @@ -5,26 +5,19 @@ module packet_verifier32 input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); - wire [7:0] ll_data; - wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; - wire [35:0] data_int; - wire src_rdy_int, dst_rdy_int; - - fifo_short #(.WIDTH(36)) fifo_short - (.clk(clk), .reset(reset), .clear(clear), - .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); - + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy; + fifo36_to_ll8 f36_to_ll8 (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), - .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .ll_data(ll_data), .ll_sof(ll_sof), .ll_eof(ll_eof), + .ll_src_rdy(ll_src_rdy), .ll_dst_rdy(ll_dst_rdy)); packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), - .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), - .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .data_i(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), + .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); endmodule // packet_verifier32 diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v index a5a477202..b3d71b4ab 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -152,7 +152,6 @@ module u1e_core .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), .debug_rx(vrf_debug) ); fifo36_mux #(.prio(0)) mux_err_stream |