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author | Josh Blum <josh@joshknows.com> | 2011-05-16 11:56:48 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-05-16 11:56:48 -0700 |
commit | 204144fa842198b99da44da11e609916406cc6ff (patch) | |
tree | 67f9553d6a504e9007fc3b84d14aa645f6ebd0b2 /fpga | |
parent | 91e32eaea25b023ec33b0efc80a653dac5a676df (diff) | |
parent | 32b0989c014bd90becdaddc3c3ba957125606f43 (diff) | |
download | uhd-204144fa842198b99da44da11e609916406cc6ff.tar.gz uhd-204144fa842198b99da44da11e609916406cc6ff.tar.bz2 uhd-204144fa842198b99da44da11e609916406cc6ff.zip |
Merge branch 'next' into use_vita_length
Diffstat (limited to 'fpga')
-rw-r--r-- | fpga/usrp2/top/u1e/u1e_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v index 8e6d74edf..d10a3ab30 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -36,7 +36,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd3; + wire [7:0] COMPAT_NUM = 8'd4; wire wb_clk = clk_fpga; wire wb_rst, global_reset; |