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| author | Martin Braun <martin.braun@ettus.com> | 2022-02-21 11:17:25 +0100 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2022-02-22 14:41:19 -0600 |
| commit | ba00ff0cf5c0ced093e0be12b3006fe2f657a58a (patch) | |
| tree | 6a1030bc21b6257d4a34f8f3e6c4cdbbc55860f1 /fpga | |
| parent | 250ef76d5034aca69e9335055f7b223f1742966f (diff) | |
| download | uhd-ba00ff0cf5c0ced093e0be12b3006fe2f657a58a.tar.gz uhd-ba00ff0cf5c0ced093e0be12b3006fe2f657a58a.tar.bz2 uhd-ba00ff0cf5c0ced093e0be12b3006fe2f657a58a.zip | |
Remove FSRU-related files
The FSRU (aka EISCAT) was never supported in UHD 4.0. The FPGA
repository never had the relevant files, and the block controller also
never existed. This removes all the corresponding files from MPM, as
well as some references from makefiles.
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/n3xx/setupenv.sh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/fpga/usrp3/top/n3xx/setupenv.sh b/fpga/usrp3/top/n3xx/setupenv.sh index bb20a330c..d3057d5ce 100644 --- a/fpga/usrp3/top/n3xx/setupenv.sh +++ b/fpga/usrp3/top/n3xx/setupenv.sh @@ -8,7 +8,6 @@ declare -A PRODUCT_ID_MAP PRODUCT_ID_MAP["N300"]="zynq/xc7z035/ffg900/-2" PRODUCT_ID_MAP["N310"]="zynq/xc7z100/ffg900/-2" PRODUCT_ID_MAP["N320"]="zynq/xc7z100/ffg900/-2" -PRODUCT_ID_MAP["EISCAT"]="zynq/xc7z100/ffg900/-2" # Set default part for simulation export ARCH=zynq |