fpga: x400: Add timed commands support for all radio ctrlport endpoints

Extends timed command support to all endpoints
addressable by the radio ctrlport interface.

  Previously supported endpoints:
    - Daughterboard GPIO interface
    - RFDC timing control
  Newly supported endpoints:
    - DIO ATR control
    - DIO SPI control
    - DIO Source control

7 files changed, 104 insertions, 182 deletions

diff --git a/fpga/usrp3/top/x400/dboards/db_gpio_interface.v b/fpga/usrp3/top/x400/dboards/db_gpio_interface.v
index 1e8cd44ee..d48650d7c 100644
--- a/fpga/usrp3/top/x400/dboards/db_gpio_interface.v
+++ b/fpga/usrp3/top/x400/dboards/db_gpio_interface.v
@@ -34,26 +34,17 @@ module db_gpio_interface (
 
   // DB state lines (domain: radio_clk)
   input  wire [ 3:0] db_state,
-
-  // time interfaces (domain: radio_clk)
-  input  wire [63:0] radio_time,
-  input  wire        radio_time_stb,
-  input  wire [ 3:0] time_ignore_bits,
-
   // Request (domain: radio_clk)
   input  wire        ctrlport_rst,
   input  wire        s_ctrlport_req_wr,
   input  wire        s_ctrlport_req_rd,
   input  wire [19:0] s_ctrlport_req_addr,
   input  wire [31:0] s_ctrlport_req_data,
-  input  wire [ 3:0] s_ctrlport_req_byte_en,
-  input  wire        s_ctrlport_req_has_time,
-  input  wire [63:0] s_ctrlport_req_time,
 
   // Response (domain: radio_clk)
   output wire        s_ctrlport_resp_ack,
-  output wire [ 1:0] s_ctrlport_resp_status,
-  output wire [31:0] s_ctrlport_resp_data,
+  output reg  [ 1:0] s_ctrlport_resp_status,
+  output reg  [31:0] s_ctrlport_resp_data,
 
   // GPIO interface (domain: pll_ref_clk)
   input  wire [19:0] gpio_in,
@@ -68,45 +59,6 @@ module db_gpio_interface (
   `include "../regmap/versioning_utils.vh"
 
   //----------------------------------------------------------------------------
-  // Timed command processing
-  //----------------------------------------------------------------------------
-  wire [19:0] ctrlport_timed_req_addr;
-  wire [31:0] ctrlport_timed_req_data;
-  wire        ctrlport_timed_req_rd;
-  wire        ctrlport_timed_req_wr;
-  wire        ctrlport_timed_resp_ack;
-  reg  [31:0] ctrlport_timed_resp_data = 0;
-  reg  [ 1:0] ctrlport_timed_resp_status = 0;
-
-  ctrlport_timer #(
-    .EXEC_LATE_CMDS(1)
-  ) ctrlport_timer_i (
-    .clk                      (radio_clk),
-    .rst                      (ctrlport_rst),
-    .time_now                 (radio_time),
-    .time_now_stb             (radio_time_stb),
-    .time_ignore_bits         (time_ignore_bits),
-    .s_ctrlport_req_wr        (s_ctrlport_req_wr),
-    .s_ctrlport_req_rd        (s_ctrlport_req_rd),
-    .s_ctrlport_req_addr      (s_ctrlport_req_addr),
-    .s_ctrlport_req_data      (s_ctrlport_req_data),
-    .s_ctrlport_req_byte_en   (s_ctrlport_req_byte_en),
-    .s_ctrlport_req_has_time  (s_ctrlport_req_has_time),
-    .s_ctrlport_req_time      (s_ctrlport_req_time),
-    .s_ctrlport_resp_ack      (s_ctrlport_resp_ack),
-    .s_ctrlport_resp_status   (s_ctrlport_resp_status),
-    .s_ctrlport_resp_data     (s_ctrlport_resp_data),
-    .m_ctrlport_req_wr        (ctrlport_timed_req_wr),
-    .m_ctrlport_req_rd        (ctrlport_timed_req_rd),
-    .m_ctrlport_req_addr      (ctrlport_timed_req_addr),
-    .m_ctrlport_req_data      (ctrlport_timed_req_data),
-    .m_ctrlport_req_byte_en   (),
-    .m_ctrlport_resp_ack      (ctrlport_timed_resp_ack),
-    .m_ctrlport_resp_status   (ctrlport_timed_resp_status),
-    .m_ctrlport_resp_data     (ctrlport_timed_resp_data)
-  );
-
-  //----------------------------------------------------------------------------
   // Clock domain crossing (radio_clk -> pll_ref_clk)
   //----------------------------------------------------------------------------
   // Radio_clk is derived from pll_ref_clk by an integer multiplier and
@@ -116,8 +68,8 @@ module db_gpio_interface (
   // them.
 
   // holding read and write flags for multiple radio_clk cycles
-  reg         ctrlport_timed_req_wr_hold = 1'b0;
-  reg         ctrlport_timed_req_rd_hold = 1'b0;
+  reg         ctrlport_req_wr_hold = 1'b0;
+  reg         ctrlport_req_rd_hold = 1'b0;
 
   reg  [19:0] ctrlport_req_addr_prc = 20'b0;
   reg  [31:0] ctrlport_req_data_prc = 32'b0;
@@ -151,41 +103,41 @@ module db_gpio_interface (
 
   always @(posedge radio_clk) begin
     if (ctrlport_req_wr_fall) begin
-      ctrlport_timed_req_wr_hold <= 1'b0;
-    end else if (ctrlport_timed_req_wr) begin
-      ctrlport_timed_req_wr_hold <= 1'b1;
+      ctrlport_req_wr_hold <= 1'b0;
+    end else if (s_ctrlport_req_wr) begin
+      ctrlport_req_wr_hold <= 1'b1;
     end
     if (ctrlport_req_rd_fall) begin
-      ctrlport_timed_req_rd_hold <= 1'b0;
-    end else if (ctrlport_timed_req_rd) begin
-      ctrlport_timed_req_rd_hold <= 1'b1;
+      ctrlport_req_rd_hold <= 1'b0;
+    end else if (s_ctrlport_req_rd) begin
+      ctrlport_req_rd_hold <= 1'b1;
     end
 
     // capture request address and data
-    if (ctrlport_timed_req_wr || ctrlport_timed_req_rd) begin
-      ctrlport_req_addr_prc <= ctrlport_timed_req_addr;
-      ctrlport_req_data_prc <= ctrlport_timed_req_data;
+    if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin
+      ctrlport_req_addr_prc <= s_ctrlport_req_addr;
+      ctrlport_req_data_prc <= s_ctrlport_req_data;
     end
   end
 
   // capture extended flags in pll_ref_clk domain
   always @(posedge pll_ref_clk) begin
-    ctrlport_req_wr_prc <= ctrlport_timed_req_wr_hold;
-    ctrlport_req_rd_prc <= ctrlport_timed_req_rd_hold;
+    ctrlport_req_wr_prc <= ctrlport_req_wr_hold;
+    ctrlport_req_rd_prc <= ctrlport_req_rd_hold;
   end
 
   // search for rising edge in response
-  reg [1:0] ctrlport_timed_ack_reg = 2'b0;
+  reg [1:0] ctrlport_resp_ack_reg = 2'b0;
   always @(posedge radio_clk) begin
-    ctrlport_timed_ack_reg = {ctrlport_timed_ack_reg[0], ctrlport_resp_ack_fall};
+    ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall};
   end
-  assign ctrlport_timed_resp_ack = ctrlport_timed_ack_reg[0] & ~ctrlport_timed_ack_reg[1];
+  assign s_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1];
 
   // capture response data
   always @(posedge radio_clk) begin
     if (ctrlport_resp_ack_fall) begin
-      ctrlport_timed_resp_status <= ctrlport_resp_status_fall;
-      ctrlport_timed_resp_data   <= ctrlport_resp_data_fall;
+      s_ctrlport_resp_status <= ctrlport_resp_status_fall;
+      s_ctrlport_resp_data   <= ctrlport_resp_data_fall;
     end
   end
 
diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
index ec5c99380..f9829ac3a 100644
--- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
+++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
@@ -24233,7 +24233,7 @@ FPGA version.<BR/>
                             <td class='l'>0x00000007</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
                             
 </td>
 
@@ -24241,12 +24241,12 @@ FPGA version.<BR/>
 
 <tr valign="top">
 
-                        <td class='value'>7</td>
+                        <td class='value'>8</td>
                         
-                            <td class='l'>0x00000007</td>
+                            <td class='l'>0x00000008</td>
                             
                             <td class="l" style="text-align: left;">
-                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR'></a>FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR</p>
+                              <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_CURRENT_VERSION_MINOR'></a>FPGA_CURRENT_VERSION_MINOR</p>
                             
 </td>
 
@@ -24254,9 +24254,9 @@ FPGA version.<BR/>
 
 <tr valign="top">
 
-                        <td class='value'>570622482</td>
+                        <td class='value'>570627860</td>
                         
-                            <td class='l'>0x22030212</td>
+                            <td class='l'>0x22031714</td>
                             
                             <td class="l" style="text-align: left;">
                               <p class="name"><a name='VERSIONING_REGS_REGMAP|FPGA_VERSION|FPGA_VERSION_LAST_MODIFIED_TIME'></a>FPGA_VERSION_LAST_MODIFIED_TIME</p>
diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
index 84a5dd7b6..2a07e17cb 100644
--- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
+++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh
@@ -83,9 +83,9 @@
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD  = 'h0;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD
   localparam FPGA_CURRENT_VERSION_MAJOR            = 'h7;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR
-  localparam FPGA_CURRENT_VERSION_MINOR            = 'h7;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
   localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR  = 'h7;  // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR
-  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h22030212;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
+  localparam FPGA_CURRENT_VERSION_MINOR            = 'h8;  // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR
+  localparam FPGA_VERSION_LAST_MODIFIED_TIME       = 'h22031714;  // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME
 
   // Enumerated type RF_CORE_100M_VERSION
   localparam RF_CORE_100M_VERSION_SIZE = 7;
diff --git a/fpga/usrp3/top/x400/rfdc_timing_control.v b/fpga/usrp3/top/x400/rfdc_timing_control.v
index 6177505f7..8cbd4759e 100644
--- a/fpga/usrp3/top/x400/rfdc_timing_control.v
+++ b/fpga/usrp3/top/x400/rfdc_timing_control.v
@@ -25,19 +25,11 @@ module rfdc_timing_control #(
   input wire clk,
   input wire rst,
 
-  // Time
-  input wire [63:0] time_now,
-  input wire        time_now_stb,
-  input wire [ 3:0] time_ignore_bits,
-
   // CtrlPort Slave (from RFNoC Radio Block)
   input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_wr,
   input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_rd,
   input  wire [ 20*NUM_DBOARDS-1:0] s_ctrlport_req_addr,
   input  wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_req_data,
-  input  wire [  4*NUM_DBOARDS-1:0] s_ctrlport_req_byte_en,
-  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_has_time,
-  input  wire [ 64*NUM_DBOARDS-1:0] s_ctrlport_req_time,
   output wire [  1*NUM_DBOARDS-1:0] s_ctrlport_resp_ack,
   output wire [  2*NUM_DBOARDS-1:0] s_ctrlport_resp_status,
   output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data,
@@ -61,43 +53,29 @@ module rfdc_timing_control #(
     for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport
 
       //-----------------------------------------------------------------------
-      // RF Reset Control
+      // CtrlPort Breakdown
       //-----------------------------------------------------------------------
 
-      wire [  1-1:0] nco_ctrlport_req_wr;
-      wire [  1-1:0] nco_ctrlport_req_rd;
-      wire [ 20-1:0] nco_ctrlport_req_addr;
-      wire [ 32-1:0] nco_ctrlport_req_data;
-      reg  [  1-1:0] nco_ctrlport_resp_ack;
-      reg  [ 32-1:0] nco_ctrlport_resp_data;
-
-      ctrlport_timer #(
-        .EXEC_LATE_CMDS (1)
-      ) ctrlport_timer_nco (
-        .clk                     (clk),
-        .rst                     (rst),
-        .time_now                (time_now),
-        .time_now_stb            (time_now_stb),
-        .time_ignore_bits        (time_ignore_bits),
-        .s_ctrlport_req_wr       (s_ctrlport_req_wr       [ 1*db+: 1]),
-        .s_ctrlport_req_rd       (s_ctrlport_req_rd       [ 1*db+: 1]),
-        .s_ctrlport_req_addr     (s_ctrlport_req_addr     [20*db+:20]),
-        .s_ctrlport_req_data     (s_ctrlport_req_data     [32*db+:32]),
-        .s_ctrlport_req_byte_en  (s_ctrlport_req_byte_en  [ 4*db+: 4]),
-        .s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]),
-        .s_ctrlport_req_time     (s_ctrlport_req_time     [64*db+:64]),
-        .s_ctrlport_resp_ack     (s_ctrlport_resp_ack     [ 1*db+: 1]),
-        .s_ctrlport_resp_status  (s_ctrlport_resp_status  [ 2*db+: 2]),
-        .s_ctrlport_resp_data    (s_ctrlport_resp_data    [32*db+:32]),
-        .m_ctrlport_req_wr       (nco_ctrlport_req_wr),
-        .m_ctrlport_req_rd       (nco_ctrlport_req_rd),
-        .m_ctrlport_req_addr     (nco_ctrlport_req_addr),
-        .m_ctrlport_req_data     (nco_ctrlport_req_data),
-        .m_ctrlport_req_byte_en  (),
-        .m_ctrlport_resp_ack     (nco_ctrlport_resp_ack),
-        .m_ctrlport_resp_status  (2'b0),
-        .m_ctrlport_resp_data    (nco_ctrlport_resp_data)
-      );
+      wire         nco_ctrlport_req_wr;
+      wire         nco_ctrlport_req_rd;
+      wire [ 19:0] nco_ctrlport_req_addr;
+      wire [ 31:0] nco_ctrlport_req_data;
+      reg          nco_ctrlport_resp_ack;
+      reg  [ 31:0] nco_ctrlport_resp_data;
+      wire [  1:0] nco_ctrlport_resp_status = 2'b0;
+
+      assign nco_ctrlport_req_wr    = s_ctrlport_req_wr   [ 1*db+: 1];
+      assign nco_ctrlport_req_rd    = s_ctrlport_req_rd   [ 1*db+: 1];
+      assign nco_ctrlport_req_addr  = s_ctrlport_req_addr [20*db+:20];
+      assign nco_ctrlport_req_data  = s_ctrlport_req_data [32*db+:32];
+
+      assign s_ctrlport_resp_ack     [ 1*db+: 1] = nco_ctrlport_resp_ack;
+      assign s_ctrlport_resp_status  [ 2*db+: 2] = nco_ctrlport_resp_data;
+      assign s_ctrlport_resp_data    [32*db+:32] = nco_ctrlport_resp_status;
+
+      //-----------------------------------------------------------------------
+      // RF Reset Control
+      //-----------------------------------------------------------------------
 
       always @(posedge clk) begin
         if (rst) begin
diff --git a/fpga/usrp3/top/x400/x4xx.v b/fpga/usrp3/top/x400/x4xx.v
index 07022a3fc..e0d932a8e 100644
--- a/fpga/usrp3/top/x400/x4xx.v
+++ b/fpga/usrp3/top/x400/x4xx.v
@@ -1467,17 +1467,11 @@ module x4xx (
         .radio_clk               (radio_clk),
         .pll_ref_clk             (pll_ref_clk),
         .db_state                (db_state[dboard_num]),
-        .radio_time              (radio_time),
-        .radio_time_stb          (radio_time_stb),
-        .time_ignore_bits        (time_ignore_bits),
         .ctrlport_rst            (radio_rst),
         .s_ctrlport_req_wr       (db_ctrlport_req_wr[dboard_num]),
         .s_ctrlport_req_rd       (db_ctrlport_req_rd[dboard_num]),
         .s_ctrlport_req_addr     (db_ctrlport_req_addr[dboard_num]),
         .s_ctrlport_req_data     (db_ctrlport_req_data[dboard_num]),
-        .s_ctrlport_req_byte_en  (db_ctrlport_req_byte_en[dboard_num]),
-        .s_ctrlport_req_has_time (db_ctrlport_req_has_time[dboard_num]),
-        .s_ctrlport_req_time     (db_ctrlport_req_time[dboard_num]),
         .s_ctrlport_resp_ack     (db_ctrlport_resp_ack[dboard_num]),
         .s_ctrlport_resp_status  (db_ctrlport_resp_status[dboard_num]),
         .s_ctrlport_resp_data    (db_ctrlport_resp_data[dboard_num]),
@@ -2181,9 +2175,6 @@ module x4xx (
     .m_ctrlport_radio_req_rd       ({ db_ctrlport_req_rd       [1], db_ctrlport_req_rd       [0] }),
     .m_ctrlport_radio_req_addr     ({ db_ctrlport_req_addr     [1], db_ctrlport_req_addr     [0] }),
     .m_ctrlport_radio_req_data     ({ db_ctrlport_req_data     [1], db_ctrlport_req_data     [0] }),
-    .m_ctrlport_radio_req_byte_en  ({ db_ctrlport_req_byte_en  [1], db_ctrlport_req_byte_en  [0] }),
-    .m_ctrlport_radio_req_has_time ({ db_ctrlport_req_has_time [1], db_ctrlport_req_has_time [0] }),
-    .m_ctrlport_radio_req_time     ({ db_ctrlport_req_time     [1], db_ctrlport_req_time     [0] }),
     .m_ctrlport_radio_resp_ack     ({ db_ctrlport_resp_ack     [1], db_ctrlport_resp_ack     [0] }),
     .m_ctrlport_radio_resp_status  ({ db_ctrlport_resp_status  [1], db_ctrlport_resp_status  [0] }),
     .m_ctrlport_radio_resp_data    ({ db_ctrlport_resp_data    [1], db_ctrlport_resp_data    [0] }),
@@ -2284,12 +2275,12 @@ endmodule
 //        <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
 //      </info>
 //      <value name="FPGA_CURRENT_VERSION_MAJOR"           integer="7"/>
-//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="7"/>
+//      <value name="FPGA_CURRENT_VERSION_MINOR"           integer="8"/>
 //      <value name="FPGA_CURRENT_VERSION_BUILD"           integer="0"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="7"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
 //      <value name="FPGA_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
-//      <value name="FPGA_VERSION_LAST_MODIFIED_TIME"      integer="0x22030212"/>
+//      <value name="FPGA_VERSION_LAST_MODIFIED_TIME"      integer="0x22031714"/>
 //    </enumeratedtype>
 //  </group>
 //</regmap>
diff --git a/fpga/usrp3/top/x400/x4xx_core.v b/fpga/usrp3/top/x400/x4xx_core.v
index eac0b8f0a..13af59e9d 100644
--- a/fpga/usrp3/top/x400/x4xx_core.v
+++ b/fpga/usrp3/top/x400/x4xx_core.v
@@ -185,9 +185,6 @@ module x4xx_core #(
   output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_rd,
   output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_radio_req_addr,
   output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_req_data,
-  output wire [  4*NUM_DBOARDS-1:0] m_ctrlport_radio_req_byte_en,
-  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_has_time,
-  output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_radio_req_time,
   input  wire [  1*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_ack,
   input  wire [  2*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_status,
   input  wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_data,
@@ -359,9 +356,6 @@ module x4xx_core #(
     .m_radio_ctrlport_req_rd          (m_ctrlport_radio_req_rd),
     .m_radio_ctrlport_req_addr        (m_ctrlport_radio_req_addr),
     .m_radio_ctrlport_req_data        (m_ctrlport_radio_req_data),
-    .m_radio_ctrlport_req_byte_en     (m_ctrlport_radio_req_byte_en),
-    .m_radio_ctrlport_req_has_time    (m_ctrlport_radio_req_has_time),
-    .m_radio_ctrlport_req_time        (m_ctrlport_radio_req_time),
     .m_radio_ctrlport_resp_ack        (m_ctrlport_radio_resp_ack),
     .m_radio_ctrlport_resp_status     (m_ctrlport_radio_resp_status),
     .m_radio_ctrlport_resp_data       (m_ctrlport_radio_resp_data),
diff --git a/fpga/usrp3/top/x400/x4xx_core_common.v b/fpga/usrp3/top/x400/x4xx_core_common.v
index 89dd49a49..633aa6925 100644
--- a/fpga/usrp3/top/x400/x4xx_core_common.v
+++ b/fpga/usrp3/top/x400/x4xx_core_common.v
@@ -124,9 +124,6 @@ module x4xx_core_common #(
   output wire [  1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_rd,
   output wire [ 20*NUM_DBOARDS-1:0] m_radio_ctrlport_req_addr,
   output wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_req_data,
-  output wire [  4*NUM_DBOARDS-1:0] m_radio_ctrlport_req_byte_en,
-  output wire [  1*NUM_DBOARDS-1:0] m_radio_ctrlport_req_has_time,
-  output wire [ 64*NUM_DBOARDS-1:0] m_radio_ctrlport_req_time,
   input  wire [  1*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_ack,
   input  wire [  2*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_status,
   input  wire [ 32*NUM_DBOARDS-1:0] m_radio_ctrlport_resp_data,
@@ -355,9 +352,6 @@ module x4xx_core_common #(
   wire [  1*NUM_DBOARDS-1:0] rf_ctrlport_req_rd;
   wire [ 20*NUM_DBOARDS-1:0] rf_ctrlport_req_addr;
   wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_req_data;
-  wire [  4*NUM_DBOARDS-1:0] rf_ctrlport_req_byte_en;
-  wire [  1*NUM_DBOARDS-1:0] rf_ctrlport_req_has_time;
-  wire [ 64*NUM_DBOARDS-1:0] rf_ctrlport_req_time;
   wire [  1*NUM_DBOARDS-1:0] rf_ctrlport_resp_ack;
   wire [  2*NUM_DBOARDS-1:0] rf_ctrlport_resp_status;
   wire [ 32*NUM_DBOARDS-1:0] rf_ctrlport_resp_data;
@@ -366,9 +360,6 @@ module x4xx_core_common #(
   wire [  1*NUM_DBOARDS-1:0] radio_dio_req_rd;
   wire [ 20*NUM_DBOARDS-1:0] radio_dio_req_addr;
   wire [ 32*NUM_DBOARDS-1:0] radio_dio_req_data;
-  wire [  4*NUM_DBOARDS-1:0] radio_dio_req_byte_en;
-  wire [  1*NUM_DBOARDS-1:0] radio_dio_req_has_time;
-  wire [ 64*NUM_DBOARDS-1:0] radio_dio_req_time;
   wire [  1*NUM_DBOARDS-1:0] radio_dio_resp_ack;
   wire [  2*NUM_DBOARDS-1:0] radio_dio_resp_status;
   wire [ 32*NUM_DBOARDS-1:0] radio_dio_resp_data;
@@ -377,9 +368,6 @@ module x4xx_core_common #(
   wire [  1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_rd;
   wire [ 20*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_addr;
   wire [ 32*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_data;
-  wire [  4*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_byte_en;
-  wire [  1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_has_time;
-  wire [ 64*NUM_DBOARDS-1:0] gpio_atr_ctrlport_req_time;
   wire [  1*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_ack;
   wire [  2*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_status;
   wire [ 32*NUM_DBOARDS-1:0] gpio_atr_ctrlport_resp_data;
@@ -388,9 +376,6 @@ module x4xx_core_common #(
   wire [  1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_rd;
   wire [ 20*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_addr;
   wire [ 32*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_data;
-  wire [  4*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_byte_en;
-  wire [  1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_has_time;
-  wire [ 64*NUM_DBOARDS-1:0] gpio_spi_ctrlport_req_time;
   wire [  1*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_ack;
   wire [  2*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_status;
   wire [ 32*NUM_DBOARDS-1:0] gpio_spi_ctrlport_resp_data;
@@ -407,6 +392,46 @@ module x4xx_core_common #(
   generate
     for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_radio_ctrlport
 
+      //----------------------------------------------------------------------------
+      // Timed command processing
+      //----------------------------------------------------------------------------
+
+      wire [19:0] ctrlport_timed_req_addr;
+      wire [31:0] ctrlport_timed_req_data;
+      wire        ctrlport_timed_req_rd;
+      wire        ctrlport_timed_req_wr;
+      wire        ctrlport_timed_resp_ack;
+      wire [31:0] ctrlport_timed_resp_data;
+      wire [ 1:0] ctrlport_timed_resp_status;
+
+      ctrlport_timer #(
+        .EXEC_LATE_CMDS(1)
+      ) ctrlport_timer_i (
+        .clk                      (radio_clk),
+        .rst                      (radio_rst),
+        .time_now                 (radio_time),
+        .time_now_stb             (sample_rx_stb),
+        .time_ignore_bits         (time_ignore_bits),
+        .s_ctrlport_req_wr        (s_radio_ctrlport_req_wr         [ 1*db+: 1]),
+        .s_ctrlport_req_rd        (s_radio_ctrlport_req_rd         [ 1*db+: 1]),
+        .s_ctrlport_req_addr      (s_radio_ctrlport_req_addr       [20*db+:20]),
+        .s_ctrlport_req_data      (s_radio_ctrlport_req_data       [32*db+:32]),
+        .s_ctrlport_req_byte_en   (s_radio_ctrlport_req_byte_en    [ 4*db+: 4]),
+        .s_ctrlport_req_has_time  (s_radio_ctrlport_req_has_time   [ 1*db+: 1]),
+        .s_ctrlport_req_time      (s_radio_ctrlport_req_time       [64*db+:64]),
+        .s_ctrlport_resp_ack      (s_radio_ctrlport_resp_ack       [ 1*db+: 1]),
+        .s_ctrlport_resp_status   (s_radio_ctrlport_resp_status    [ 2*db+: 2]),
+        .s_ctrlport_resp_data     (s_radio_ctrlport_resp_data      [32*db+:32]),
+        .m_ctrlport_req_wr        (ctrlport_timed_req_wr),
+        .m_ctrlport_req_rd        (ctrlport_timed_req_rd),
+        .m_ctrlport_req_addr      (ctrlport_timed_req_addr),
+        .m_ctrlport_req_data      (ctrlport_timed_req_data),
+        .m_ctrlport_req_byte_en   (),
+        .m_ctrlport_resp_ack      (ctrlport_timed_resp_ack),
+        .m_ctrlport_resp_status   (ctrlport_timed_resp_status),
+        .m_ctrlport_resp_data     (ctrlport_timed_resp_data)
+      );
+
       //-----------------------------------------------------------------------
       // Radio Block CtrlPort Splitter
       //-----------------------------------------------------------------------
@@ -448,16 +473,16 @@ module x4xx_core_common #(
       ) ctrlport_decoder_param_i (
         .ctrlport_clk            (  radio_clk ),
         .ctrlport_rst            (  radio_rst ),
-        .s_ctrlport_req_wr       (  s_radio_ctrlport_req_wr         [ 1*db+: 1] ),
-        .s_ctrlport_req_rd       (  s_radio_ctrlport_req_rd         [ 1*db+: 1] ),
-        .s_ctrlport_req_addr     (  s_radio_ctrlport_req_addr       [20*db+:20] ),
-        .s_ctrlport_req_data     (  s_radio_ctrlport_req_data       [32*db+:32] ),
-        .s_ctrlport_req_byte_en  (  s_radio_ctrlport_req_byte_en    [ 4*db+: 4] ),
-        .s_ctrlport_req_has_time (  s_radio_ctrlport_req_has_time   [ 1*db+: 1] ),
-        .s_ctrlport_req_time     (  s_radio_ctrlport_req_time       [64*db+:64] ),
-        .s_ctrlport_resp_ack     (  s_radio_ctrlport_resp_ack       [ 1*db+: 1] ),
-        .s_ctrlport_resp_status  (  s_radio_ctrlport_resp_status    [ 2*db+: 2] ),
-        .s_ctrlport_resp_data    (  s_radio_ctrlport_resp_data      [32*db+:32] ),
+        .s_ctrlport_req_wr       (  ctrlport_timed_req_wr),
+        .s_ctrlport_req_rd       (  ctrlport_timed_req_rd),
+        .s_ctrlport_req_addr     (  ctrlport_timed_req_addr),
+        .s_ctrlport_req_data     (  ctrlport_timed_req_data),
+        .s_ctrlport_req_byte_en  (  4'hF),
+        .s_ctrlport_req_has_time (  1'b0),
+        .s_ctrlport_req_time     (  64'h0),
+        .s_ctrlport_resp_ack     (  ctrlport_timed_resp_ack),
+        .s_ctrlport_resp_status  (  ctrlport_timed_resp_status),
+        .s_ctrlport_resp_data    (  ctrlport_timed_resp_data),
         .m_ctrlport_req_wr       ({ gpio_spi_ctrlport_req_wr        [ 1*db+: 1],
                                     radio_dio_req_wr                [ 1*db+: 1],
                                     gpio_atr_ctrlport_req_wr        [ 1*db+: 1],
@@ -478,21 +503,9 @@ module x4xx_core_common #(
                                     gpio_atr_ctrlport_req_data      [32*db+:32],
                                     rf_ctrlport_req_data            [32*db+:32],
                                     m_radio_ctrlport_req_data       [32*db+:32] }),
-        .m_ctrlport_req_byte_en  ({ gpio_spi_ctrlport_req_byte_en   [ 4*db+: 4],
-                                    radio_dio_req_byte_en           [ 4*db+: 4],
-                                    gpio_atr_ctrlport_req_byte_en   [ 4*db+: 4],
-                                    rf_ctrlport_req_byte_en         [ 4*db+: 4],
-                                    m_radio_ctrlport_req_byte_en    [ 4*db+: 4] }),
-        .m_ctrlport_req_has_time ({ gpio_spi_ctrlport_req_has_time  [ 1*db+: 1],
-                                    radio_dio_req_has_time          [ 1*db+: 1],
-                                    gpio_atr_ctrlport_req_has_time  [ 1*db+: 1],
-                                    rf_ctrlport_req_has_time        [ 1*db+: 1],
-                                    m_radio_ctrlport_req_has_time   [ 1*db+: 1] }),
-        .m_ctrlport_req_time     ({ gpio_spi_ctrlport_req_time      [64*db+:64],
-                                    radio_dio_req_time              [64*db+:64],
-                                    gpio_atr_ctrlport_req_time      [64*db+:64],
-                                    rf_ctrlport_req_time            [64*db+:64],
-                                    m_radio_ctrlport_req_time       [64*db+:64] }),
+        .m_ctrlport_req_byte_en  (),
+        .m_ctrlport_req_has_time (),
+        .m_ctrlport_req_time     (),
         .m_ctrlport_resp_ack     ({ gpio_spi_ctrlport_resp_ack      [ 1*db+: 1],
                                     radio_dio_resp_ack              [ 1*db+: 1],
                                     gpio_atr_ctrlport_resp_ack      [ 1*db+: 1],
@@ -565,16 +578,10 @@ module x4xx_core_common #(
   ) rfdc_timing_control_i (
     .clk                              (radio_clk),
     .rst                              (radio_rst),
-    .time_now                         (radio_time),
-    .time_now_stb                     (sample_rx_stb),
-    .time_ignore_bits                 (time_ignore_bits),
     .s_ctrlport_req_wr                (rf_ctrlport_req_wr),
     .s_ctrlport_req_rd                (rf_ctrlport_req_rd),
     .s_ctrlport_req_addr              (rf_ctrlport_req_addr),
     .s_ctrlport_req_data              (rf_ctrlport_req_data),
-    .s_ctrlport_req_byte_en           (rf_ctrlport_req_byte_en),
-    .s_ctrlport_req_has_time          (rf_ctrlport_req_has_time),
-    .s_ctrlport_req_time              (rf_ctrlport_req_time),
     .s_ctrlport_resp_ack              (rf_ctrlport_resp_ack),
     .s_ctrlport_resp_status           (rf_ctrlport_resp_status),
     .s_ctrlport_resp_data             (rf_ctrlport_resp_data),