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authorAshish Chaudhari <ashish@ettus.com>2014-08-20 09:31:33 -0700
committerAshish Chaudhari <ashish@ettus.com>2014-08-20 09:31:33 -0700
commit9fb6c2919ad9e7e736c837186861b362ba80cdfa (patch)
tree576291345a63a4bfd1db7c4443c36551c924de27 /fpga/usrp3
parent72eae0503393966dfb2b961835ad1f9c5e5265e7 (diff)
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fpga: Added FPGA code for B200 AD9361 host driver addition
Diffstat (limited to 'fpga/usrp3')
-rw-r--r--fpga/usrp3/top/b200/b200.v25
-rw-r--r--fpga/usrp3/top/b200/b200_core.v2
2 files changed, 19 insertions, 8 deletions
diff --git a/fpga/usrp3/top/b200/b200.v b/fpga/usrp3/top/b200/b200.v
index b25c02bdf..585d5030e 100644
--- a/fpga/usrp3/top/b200/b200.v
+++ b/fpga/usrp3/top/b200/b200.v
@@ -179,16 +179,27 @@ module b200 (
///////////////////////////////////////////////////////////////////////
// SPI connections
///////////////////////////////////////////////////////////////////////
- wire mosi, miso, sclk; wire [7:0] sen;
- assign cat_ce = sen[0] & fx3_ce;
- assign cat_mosi = (~sen[0] & mosi) | (~fx3_ce & fx3_mosi);
- assign cat_sclk = (~sen[0] & sclk) | (~fx3_ce & fx3_sclk);
- assign miso = cat_miso;
- assign fx3_miso = ~fx3_ce & cat_miso;
- assign pll_ce = sen[1];
+ wire mosi, miso, sclk;
+ wire [7:0] sen;
+
+ //AD9361 Slave
+ assign cat_ce = sen[0];
+ assign cat_mosi = ~sen[0] & mosi;
+ assign cat_sclk = ~sen[0] & sclk;
+ assign miso = cat_miso; //PLL does not have a miso
+
+ //ADF4001 Slave
+ assign pll_ce = sen[1];
assign pll_mosi = ~sen[1] & mosi;
assign pll_sclk = ~sen[1] & sclk;
+ //FX3 Master
+ //The following signals are routed to the FX3 and were used by an obsolete
+ //bit-banging SPI engine.
+ // fx3_ce, fx3_sclk, fx3_mosi <Unused>
+ assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
+ //direction of this pin in the FX3
+
///////////////////////////////////////////////////////////////////////
// bus signals
///////////////////////////////////////////////////////////////////////
diff --git a/fpga/usrp3/top/b200/b200_core.v b/fpga/usrp3/top/b200/b200_core.v
index dc8baba4f..ec8d0ff5a 100644
--- a/fpga/usrp3/top/b200/b200_core.v
+++ b/fpga/usrp3/top/b200/b200_core.v
@@ -72,7 +72,7 @@ module b200_core
localparam SR_CORE_READBACK = 8'd32;
localparam SR_CORE_GPSDO_ST = 8'd40;
localparam SR_CORE_PPS_SEL = 8'd48;
- localparam COMPAT_MAJOR = 16'h0003;
+ localparam COMPAT_MAJOR = 16'h0004;
localparam COMPAT_MINOR = 16'h0000;
/*******************************************************************