fpga: n3xx: rh: cpld: Refactor CPLD build process

6 files changed, 119 insertions, 24 deletions

diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore b/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore
new file mode 100644
index 000000000..fcdcdf540
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/.gitignore
@@ -0,0 +1,7 @@
+# Ignore Quartus generated files upon project opening.
+*.qws
+db/
+incremental_db/
+output_files/
+*.sopcinfo
+build/
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
index ff1598894..c71d49052 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile
@@ -1,27 +1,78 @@
 #
-# Copyright 2018 Ettus Research, a National Instruments Company
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
 #
 
-.PHONY: all clean
+# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
+##-------------------
+##USRP N32x CPLD Help
+##-------------------
+##Usage:
+## make <Targets> <Options>
+##
+##Output:
+## build/usrp_n320_rh_cpld.pof:  Bitstream to use with JTAG programmer
+## build/usrp_n320_rh_cpld.svf:  Bitstream to use with PS JTAG engine
 
-SRCS=rhodium_top.qpf rhodium_top.qsf rhodium_top.sdc rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
-SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
-SHORT_HASH=$(addprefix GIT_HASH=,$(shell ../../../../../tools/scripts/git-hash.sh))
+# Definitions
+10M04_ID = "10M04SAU169I7G"
+
+TARGET = bin
+TOP ?= rhodium_top
+
+# quartus_build($1=Device, $2=Definitions)
+quartus_build = make -f Makefile.cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
+
+# post_build($1=Artifact Name)
+ifeq ($(TARGET),bin)
+	post_build = @\
+		mkdir -p build/; \
+		echo "Exporting bitstream files..."; \
+		cp build-$@/output_files/$(TOP).pof                      build/$(1).pof; \
+		cp build-$@/output_files/$(TOP).svf                      build/$(1).svf; \
+		echo -ne "\n\n---- Make: CPLD ready!\n"; \
+		echo -ne "     Use build/$(1).pof via JTAG programmer or\n"; \
+		echo -ne "         build/$(1).svf via PS JTAG-engine\n";
+else
+	post_build = @echo "Skipping bitfile export."
+endif
+
+##
+##Supported Targets
+##-----------------
 
-all: cpld-rhodium-revb.svf
+all:              N320_CPLD_10M04 ##(Default target)
 
-output_files/rhodium_top.pof: $(SRCS)
-	quartus_map rhodium_top --verilog_macro="$(SHORT_HASH)"
-	quartus_fit rhodium_top
-	quartus_asm rhodium_top
-	quartus_sta rhodium_top
+##N320_CPLD_10M04:  N320/1 CPLD targeted to 10M04SAU169I7G.
+N320_CPLD_10M04:
+	$(call quartus_build,$(10M04_ID),$(DEFS))
+	$(call post_build,"usrp_n320_rh_cpld")
 
-cpld-rhodium-revb.svf: output_files/rhodium_top.pof
-	quartus_cpf --convert --frequency 10.0MHz --voltage 2.5 --operation p $? $@
+clean:            ##Clean up all target build outputs.
+	@echo -ne "\nCleaning targets and git repo...\n";
+	@rm -rf build-N320_CPLD*
+	@rm -rf build
+	@git clean -Xdf
 
-clean:
-	rm -rf db incremental_db output_files simulation cpld-rhodium-revb.svf
+cleanall:         ##Clean up all target and ip build outputs.
+	@echo -ne "\nCleaning targets, IP, and git repo...\n";
+	@rm -rf build-N320_CPLD*
+	@rm -rf build
+	@rm -rf build-ip
+	@git clean -Xdf
+
+help:             ##Show this help message.
+	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
+
+
+SIM_SRCS=rh_tb.v rhodium_top.v rhodium_gain_ctrl.v rhodium_gain_table.v rhodium_lo_gain.v
 
 a.out: $(SIM_SRCS)
 	iverilog -tvvp -D$(SHORT_HASH) -s rh_tb $(SIM_SRCS)
 
+
+##
+##Supported Options
+##-----------------
+##
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc
new file mode 100644
index 000000000..aa2a1c325
--- /dev/null
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/Makefile.cpld.inc
@@ -0,0 +1,36 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+##################################################
+# Project Setup
+##################################################
+# TOP_MODULE = <Input arg>
+# NAME = <Input arg>
+# PART_ID = <Input arg>
+# ARCH = <Input arg>
+
+##################################################
+# Include other makefiles
+##################################################
+
+PROJECT_DIR = $(abspath .)
+BASE_DIR = $(abspath ../../../..)
+include $(BASE_DIR)/../tools/make/quartus_design_builder.mak
+
+# Define VERILOG_DEFS for macros definition
+VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF)
+
+bin: .prereqs
+	$(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),,0)
+	@\
+	pushd $(BUILD_DIR); \
+	echo "Converting bitfile to svf format..."; \
+	quartus_cpf --convert \
+		--frequency 10.0MHz \
+		--voltage 2.5       \
+		--operation p       \
+		output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE).svf; \
+	popd;
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
index 5e1bf4d57..5e1bf4d57 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qpf
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qpf
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf
index e94f0bbc8..4e4ce9e88 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.qsf
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/quartus/rhodium_top.qsf
@@ -286,14 +286,15 @@ set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
 set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
 set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
 set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name VERILOG_FILE rhodium_top.v
-set_global_assignment -name VERILOG_FILE rhodium_gain_ctrl.v
-set_global_assignment -name VERILOG_FILE rhodium_gain_table.v
-set_global_assignment -name VERILOG_FILE rhodium_lo_gain.v
-set_global_assignment -name VERILOG_FILE rh_tb.v
-set_global_assignment -name EDA_TEST_BENCH_FILE rh_tb.v -section_id rh_tb
-
+set_global_assignment -name VERILOG_FILE ../rhodium_top.v
+set_global_assignment -name VERILOG_FILE ../rhodium_gain_ctrl.v
+set_global_assignment -name VERILOG_FILE ../rhodium_gain_table.v
+set_global_assignment -name VERILOG_FILE ../rhodium_lo_gain.v
+set_global_assignment -name VERILOG_FILE ../rh_tb.v
+set_global_assignment -name EDA_TEST_BENCH_FILE ../rh_tb.v -section_id rh_tb
+set_global_assignment -name SDC_FILE ../rhodium_top.sdc
 
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
 set_global_assignment -name ENABLE_OCT_DONE OFF
 set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
diff --git a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
index 1d0d640da..6a23f7520 100644
--- a/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
+++ b/fpga/usrp3/top/n3xx/dboards/rh/cpld/rhodium_top.v
@@ -128,9 +128,9 @@ output    Cal_iso_Sw_Ctrl
 
 /* PS SPI */
 
-localparam GIT_HASH = 36'h`GIT_HASH;
+localparam GIT_HASH = `GIT_HASH;
 localparam PROD_SIGNATURE   = 16'h0045; // Product signature (Rhodium atomic number in BCD)
-localparam REVISION_MINOR   = 16'h0002;
+localparam REVISION_MINOR   = 16'h0003;
 localparam REVISION_MAJOR   = 16'h0004;
 localparam CPLD_BUILD_LSB   = GIT_HASH[15:0]; // Build code LSB
 localparam CPLD_BUILD_MSB   = GIT_HASH[31:16]; // Build code MSB