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authorWade Fife <wade.fife@ettus.com>2022-03-29 19:11:54 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2022-03-31 13:51:23 -0700
commit002ff9698e09b94c396736613e493f79e9c56442 (patch)
tree91680b09b654a0a53d7ee94f51c24e3653863ac1 /fpga/usrp3
parent07ee9ab75172beca11c6d68dd2daeb586ef2c3e7 (diff)
downloaduhd-002ff9698e09b94c396736613e493f79e9c56442.tar.gz
uhd-002ff9698e09b94c396736613e493f79e9c56442.tar.bz2
uhd-002ff9698e09b94c396736613e493f79e9c56442.zip
fpga: Update all RFNoC images
Diffstat (limited to 'fpga/usrp3')
-rw-r--r--fpga/usrp3/top/e31x/e310_rfnoc_image_core.v62
-rw-r--r--fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh4
-rw-r--r--fpga/usrp3/top/e31x/e310_static_router.hex2
-rw-r--r--fpga/usrp3/top/e320/e320_rfnoc_image_core.v82
-rw-r--r--fpga/usrp3/top/e320/e320_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/n3xx/n300_bist_image_core.v56
-rw-r--r--fpga/usrp3/top/n3xx/n300_bist_image_core.vh4
-rw-r--r--fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v62
-rw-r--r--fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/n3xx/n310_bist_image_core.v76
-rw-r--r--fpga/usrp3/top/n3xx/n310_bist_image_core.vh4
-rw-r--r--fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v98
-rw-r--r--fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/n3xx/n320_bist_image_core.v104
-rw-r--r--fpga/usrp3/top/n3xx/n320_bist_image_core.vh4
-rw-r--r--fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v96
-rw-r--r--fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/x300/x300_rfnoc_image_core.v96
-rw-r--r--fpga/usrp3/top/x300/x300_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/x300/x310_rfnoc_image_core.v100
-rw-r--r--fpga/usrp3/top/x300/x310_rfnoc_image_core.vh8
-rw-r--r--fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v14
-rw-r--r--fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v42
-rw-r--r--fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v6
-rw-r--r--fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh6
-rw-r--r--fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v4
-rw-r--r--fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh4
29 files changed, 508 insertions, 468 deletions
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
index 81c678400..ac479e2d9 100644
--- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-07T19:18:27.980096
+// File generated on: 2022-03-29T22:54:33.806116
// Source: e310_rfnoc_image_core.yml
-// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
+// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84
//
`default_nettype none
@@ -38,7 +38,7 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
- // ctrlport_radio
+ // ctrlport
output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 0:0] m_ctrlport_req_rd,
output wire [ 19:0] m_ctrlport_req_addr,
@@ -49,19 +49,19 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 31:0] m_ctrlport_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio
- input wire [ 63:0] radio_rx_data,
- input wire [ 1:0] radio_rx_stb,
- output wire [ 1:0] radio_rx_running,
- output wire [ 63:0] radio_tx_data,
- input wire [ 1:0] radio_tx_stb,
- output wire [ 1:0] radio_tx_running,
+ // radio
+ input wire [ 255:0] radio_rx_data,
+ input wire [ 7:0] radio_rx_stb,
+ output wire [ 7:0] radio_rx_running,
+ output wire [ 255:0] radio_tx_data,
+ input wire [ 7:0] radio_tx_stb,
+ output wire [ 7:0] radio_tx_running,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -414,7 +414,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -425,20 +425,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -490,16 +492,16 @@ module rfnoc_image_core #(
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready;
- assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
- assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
- assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
- assign m_ep1_out0_tready = s_radio0_in_1_tready;
-
assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready;
+ assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
+ assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
+ assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
+ assign m_ep1_out0_tready = s_radio0_in_1_tready;
+
assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh
index 8ea5b7c45..777378b79 100644
--- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-07T19:18:28.012652
+// File generated on: 2022-03-29T22:54:33.840276
// Source: e310_rfnoc_image_core.yml
-// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
+// Source SHA256: 8e0bdf84e7b65cbc1ad575d1d0a2fdcc33632fe69e8ca22057c0298321d8ad84
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/e31x/e310_static_router.hex b/fpga/usrp3/top/e31x/e310_static_router.hex
index 3a9dfa282..a13f8dc6b 100644
--- a/fpga/usrp3/top/e31x/e310_static_router.hex
+++ b/fpga/usrp3/top/e31x/e310_static_router.hex
@@ -1,5 +1,5 @@
00000004
004000c0
-008000c1
00c00040
+008000c1
00c10080
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
index 928a26a60..229f6fdb2 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:10.699215
+// File generated on: 2022-03-29T22:54:33.413161
// Source: e320_rfnoc_image_core.yml
-// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
+// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
//
`default_nettype none
@@ -38,7 +38,7 @@ module rfnoc_image_core #(
// IO ports /////////////////////////
- // ctrl_port
+ // ctrlport
output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 0:0] m_ctrlport_req_rd,
output wire [ 19:0] m_ctrlport_req_addr,
@@ -49,19 +49,19 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_resp_ack,
input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 31:0] m_ctrlport_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio
- input wire [ 63:0] radio_rx_data,
- input wire [ 1:0] radio_rx_stb,
- output wire [ 1:0] radio_rx_running,
- output wire [ 63:0] radio_tx_data,
- input wire [ 1:0] radio_tx_stb,
- output wire [ 1:0] radio_tx_running,
+ // radio
+ input wire [ 255:0] radio_rx_data,
+ input wire [ 7:0] radio_rx_stb,
+ output wire [ 7:0] radio_rx_running,
+ output wire [ 255:0] radio_tx_data,
+ input wire [ 7:0] radio_tx_stb,
+ output wire [ 7:0] radio_tx_running,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -679,7 +679,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -690,20 +690,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -763,7 +765,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] fifo0_axi_rst;
wire [ 3:0] fifo0_m_axi_awid;
- wire [ 127:0] fifo0_m_axi_awaddr;
+ wire [ 191:0] fifo0_m_axi_awaddr;
wire [ 31:0] fifo0_m_axi_awlen;
wire [ 11:0] fifo0_m_axi_awsize;
wire [ 7:0] fifo0_m_axi_awburst;
@@ -775,8 +777,8 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_awuser;
wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 3:0] fifo0_m_axi_awready;
- wire [ 255:0] fifo0_m_axi_wdata;
- wire [ 31:0] fifo0_m_axi_wstrb;
+ wire [2047:0] fifo0_m_axi_wdata;
+ wire [ 255:0] fifo0_m_axi_wstrb;
wire [ 3:0] fifo0_m_axi_wlast;
wire [ 3:0] fifo0_m_axi_wuser;
wire [ 3:0] fifo0_m_axi_wvalid;
@@ -787,7 +789,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 3:0] fifo0_m_axi_bready;
wire [ 3:0] fifo0_m_axi_arid;
- wire [ 127:0] fifo0_m_axi_araddr;
+ wire [ 191:0] fifo0_m_axi_araddr;
wire [ 31:0] fifo0_m_axi_arlen;
wire [ 11:0] fifo0_m_axi_arsize;
wire [ 7:0] fifo0_m_axi_arburst;
@@ -800,7 +802,7 @@ module rfnoc_image_core #(
wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 3:0] fifo0_m_axi_arready;
wire [ 3:0] fifo0_m_axi_rid;
- wire [ 255:0] fifo0_m_axi_rdata;
+ wire [2047:0] fifo0_m_axi_rdata;
wire [ 7:0] fifo0_m_axi_rresp;
wire [ 3:0] fifo0_m_axi_rlast;
wire [ 3:0] fifo0_m_axi_ruser;
@@ -810,12 +812,14 @@ module rfnoc_image_core #(
rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (5),
.CHDR_W (CHDR_W),
+ .NUM_PORTS (2),
.MEM_ADDR_W (31),
.MEM_DATA_W (64),
.MEM_CLK_RATE (300e6),
.FIFO_ADDR_BASE ({31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF}),
- .NUM_PORTS (2),
+ .IN_FIFO_SIZE (),
+ .OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_3 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -983,13 +987,6 @@ module rfnoc_image_core #(
assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
- assign radio0_radio_rx_data = radio_rx_data;
- assign radio0_radio_rx_stb = radio_rx_stb;
- assign radio_rx_running = radio0_radio_rx_running;
- assign radio_tx_data = radio0_radio_tx_data;
- assign radio0_radio_tx_stb = radio_tx_stb;
- assign radio_tx_running = radio0_radio_tx_running;
-
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -1036,6 +1033,13 @@ module rfnoc_image_core #(
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
+ assign radio0_radio_rx_data = radio_rx_data;
+ assign radio0_radio_rx_stb = radio_rx_stb;
+ assign radio_rx_running = radio0_radio_rx_running;
+ assign radio_tx_data = radio0_radio_tx_data;
+ assign radio0_radio_tx_stb = radio_tx_stb;
+ assign radio_tx_running = radio0_radio_tx_running;
+
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
diff --git a/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh b/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
index 7e7b3f72d..a00d17d2c 100644
--- a/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/e320/e320_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:10.746455
+// File generated on: 2022-03-29T22:54:33.447436
// Source: e320_rfnoc_image_core.yml
-// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
+// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.v b/fpga/usrp3/top/n3xx/n300_bist_image_core.v
index 6b1aeb2a2..392e940e1 100644
--- a/fpga/usrp3/top/n3xx/n300_bist_image_core.v
+++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.033343
+// File generated on: 2022-03-29T22:54:29.701839
// Source: n300_bist_image_core.yml
-// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
+// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
//
`default_nettype none
@@ -49,15 +49,15 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -590,7 +590,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -601,20 +601,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -727,6 +729,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
+ .IN_FIFO_SIZE (),
+ .OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -880,13 +884,6 @@ module rfnoc_image_core #(
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
- assign radio0_radio_rx_data = radio_rx_data_radio0;
- assign radio0_radio_rx_stb = radio_rx_stb_radio0;
- assign radio_rx_running_radio0 = radio0_radio_rx_running;
- assign radio_tx_data_radio0 = radio0_radio_tx_data;
- assign radio0_radio_tx_stb = radio_tx_stb_radio0;
- assign radio_tx_running_radio0 = radio0_radio_tx_running;
-
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -933,6 +930,13 @@ module rfnoc_image_core #(
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
+ assign radio0_radio_rx_data = radio_rx_data_radio0;
+ assign radio0_radio_rx_stb = radio_rx_stb_radio0;
+ assign radio_rx_running_radio0 = radio0_radio_rx_running;
+ assign radio_tx_data_radio0 = radio0_radio_tx_data;
+ assign radio0_radio_tx_stb = radio_tx_stb_radio0;
+ assign radio_tx_running_radio0 = radio0_radio_tx_running;
+
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.vh b/fpga/usrp3/top/n3xx/n300_bist_image_core.vh
index cbb2bc607..367981b0a 100644
--- a/fpga/usrp3/top/n3xx/n300_bist_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n300_bist_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.065455
+// File generated on: 2022-03-29T22:54:29.736285
// Source: n300_bist_image_core.yml
-// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
+// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
index 19807fa9b..6fc97415f 100644
--- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:08.459279
+// File generated on: 2022-03-29T22:54:30.938217
// Source: n300_rfnoc_image_core.yml
-// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
+// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
//
`default_nettype none
@@ -49,19 +49,19 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -688,7 +688,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -699,20 +699,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -772,7 +774,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
- wire [ 127:0] replay0_m_axi_awaddr;
+ wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -784,8 +786,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
- wire [ 255:0] replay0_m_axi_wdata;
- wire [ 31:0] replay0_m_axi_wstrb;
+ wire [2047:0] replay0_m_axi_wdata;
+ wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -796,7 +798,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
- wire [ 127:0] replay0_m_axi_araddr;
+ wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -809,7 +811,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
- wire [ 255:0] replay0_m_axi_rdata;
+ wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
diff --git a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh
index 4c2d73748..41c8f6492 100644
--- a/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n300_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:08.505495
+// File generated on: 2022-03-29T22:54:30.972437
// Source: n300_rfnoc_image_core.yml
-// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
+// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.v b/fpga/usrp3/top/n3xx/n310_bist_image_core.v
index 9fd9d7f9e..dcca84416 100644
--- a/fpga/usrp3/top/n3xx/n310_bist_image_core.v
+++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.473664
+// File generated on: 2022-03-29T22:54:30.114198
// Source: n310_bist_image_core.yml
-// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
+// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
//
`default_nettype none
@@ -60,22 +60,22 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
- // x300_radio1
- input wire [ 63:0] radio_rx_data_radio1,
- input wire [ 1:0] radio_rx_stb_radio1,
- output wire [ 1:0] radio_rx_running_radio1,
- output wire [ 63:0] radio_tx_data_radio1,
- input wire [ 1:0] radio_tx_stb_radio1,
- output wire [ 1:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -766,7 +766,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -777,20 +777,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -847,7 +849,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -858,20 +860,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // x300_radio
- wire [ 63:0] radio1_radio_rx_data;
- wire [ 1:0] radio1_radio_rx_stb;
- wire [ 1:0] radio1_radio_rx_running;
- wire [ 63:0] radio1_radio_tx_data;
- wire [ 1:0] radio1_radio_tx_stb;
- wire [ 1:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -984,6 +988,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
+ .IN_FIFO_SIZE (),
+ .OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.vh b/fpga/usrp3/top/n3xx/n310_bist_image_core.vh
index 5336473e0..e7fb634b3 100644
--- a/fpga/usrp3/top/n3xx/n310_bist_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n310_bist_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.506549
+// File generated on: 2022-03-29T22:54:30.148839
// Source: n310_bist_image_core.yml
-// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
+// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
index 63fdc6b70..b9dc05180 100644
--- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:09.232810
+// File generated on: 2022-03-29T22:54:31.355138
// Source: n310_rfnoc_image_core.yml
-// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
+// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
//
`default_nettype none
@@ -60,26 +60,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
- // x300_radio1
- input wire [ 63:0] radio_rx_data_radio1,
- input wire [ 1:0] radio_rx_stb_radio1,
- output wire [ 1:0] radio_rx_running_radio1,
- output wire [ 63:0] radio_tx_data_radio1,
- input wire [ 1:0] radio_tx_stb_radio1,
- output wire [ 1:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -1026,7 +1026,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -1037,20 +1037,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1197,7 +1199,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -1208,20 +1210,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // x300_radio
- wire [ 63:0] radio1_radio_rx_data;
- wire [ 1:0] radio1_radio_rx_stb;
- wire [ 1:0] radio1_radio_rx_running;
- wire [ 63:0] radio1_radio_tx_data;
- wire [ 1:0] radio1_radio_tx_stb;
- wire [ 1:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1281,7 +1285,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
- wire [ 127:0] replay0_m_axi_awaddr;
+ wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -1293,8 +1297,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
- wire [ 255:0] replay0_m_axi_wdata;
- wire [ 31:0] replay0_m_axi_wstrb;
+ wire [2047:0] replay0_m_axi_wdata;
+ wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -1305,7 +1309,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
- wire [ 127:0] replay0_m_axi_araddr;
+ wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1318,7 +1322,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
- wire [ 255:0] replay0_m_axi_rdata;
+ wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
@@ -1329,8 +1333,8 @@ module rfnoc_image_core #(
.THIS_PORTID (8),
.CHDR_W (CHDR_W),
.NUM_PORTS (4),
- .MEM_ADDR_W (31),
.MEM_DATA_W (64),
+ .MEM_ADDR_W (31),
.MTU (MTU)
) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
diff --git a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh
index 9ea3cafc5..66c414d77 100644
--- a/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n310_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:09.279594
+// File generated on: 2022-03-29T22:54:31.389520
// Source: n310_rfnoc_image_core.yml
-// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
+// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.v b/fpga/usrp3/top/n3xx/n320_bist_image_core.v
index 11055f870..a3f0c406a 100644
--- a/fpga/usrp3/top/n3xx/n320_bist_image_core.v
+++ b/fpga/usrp3/top/n3xx/n320_bist_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.909428
+// File generated on: 2022-03-29T22:54:30.534235
// Source: n320_bist_image_core.yml
-// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
+// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
//
`default_nettype none
@@ -60,22 +60,22 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // radio_ch0
- input wire [ 31:0] radio_rx_data_radio0,
- input wire [ 0:0] radio_rx_stb_radio0,
- output wire [ 0:0] radio_rx_running_radio0,
- output wire [ 31:0] radio_tx_data_radio0,
- input wire [ 0:0] radio_tx_stb_radio0,
- output wire [ 0:0] radio_tx_running_radio0,
- // radio_ch1
- input wire [ 31:0] radio_rx_data_radio1,
- input wire [ 0:0] radio_rx_stb_radio1,
- output wire [ 0:0] radio_rx_running_radio1,
- output wire [ 31:0] radio_tx_data_radio1,
- input wire [ 0:0] radio_tx_stb_radio1,
- output wire [ 0:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -612,7 +612,7 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -623,20 +623,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // radio_iface
- wire [ 31:0] radio0_radio_rx_data;
- wire [ 0:0] radio0_radio_rx_stb;
- wire [ 0:0] radio0_radio_rx_running;
- wire [ 31:0] radio0_radio_tx_data;
- wire [ 0:0] radio0_radio_tx_stb;
- wire [ 0:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -693,7 +695,7 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -704,20 +706,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // radio_iface
- wire [ 31:0] radio1_radio_rx_data;
- wire [ 0:0] radio1_radio_rx_stb;
- wire [ 0:0] radio1_radio_rx_running;
- wire [ 31:0] radio1_radio_tx_data;
- wire [ 0:0] radio1_radio_tx_stb;
- wire [ 0:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -830,6 +834,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
+ .IN_FIFO_SIZE (),
+ .OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -995,20 +1001,6 @@ module rfnoc_image_core #(
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
- assign radio0_radio_rx_data = radio_rx_data_radio0;
- assign radio0_radio_rx_stb = radio_rx_stb_radio0;
- assign radio_rx_running_radio0 = radio0_radio_rx_running;
- assign radio_tx_data_radio0 = radio0_radio_tx_data;
- assign radio0_radio_tx_stb = radio_tx_stb_radio0;
- assign radio_tx_running_radio0 = radio0_radio_tx_running;
-
- assign radio1_radio_rx_data = radio_rx_data_radio1;
- assign radio1_radio_rx_stb = radio_rx_stb_radio1;
- assign radio_rx_running_radio1 = radio1_radio_rx_running;
- assign radio_tx_data_radio1 = radio1_radio_tx_data;
- assign radio1_radio_tx_stb = radio_tx_stb_radio1;
- assign radio_tx_running_radio1 = radio1_radio_tx_running;
-
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -1055,6 +1047,20 @@ module rfnoc_image_core #(
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
+ assign radio0_radio_rx_data = radio_rx_data_radio0;
+ assign radio0_radio_rx_stb = radio_rx_stb_radio0;
+ assign radio_rx_running_radio0 = radio0_radio_rx_running;
+ assign radio_tx_data_radio0 = radio0_radio_tx_data;
+ assign radio0_radio_tx_stb = radio_tx_stb_radio0;
+ assign radio_tx_running_radio0 = radio0_radio_tx_running;
+
+ assign radio1_radio_rx_data = radio_rx_data_radio1;
+ assign radio1_radio_rx_stb = radio_rx_stb_radio1;
+ assign radio_rx_running_radio1 = radio1_radio_rx_running;
+ assign radio_tx_data_radio1 = radio1_radio_tx_data;
+ assign radio1_radio_tx_stb = radio_tx_stb_radio1;
+ assign radio_tx_running_radio1 = radio1_radio_tx_running;
+
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.vh b/fpga/usrp3/top/n3xx/n320_bist_image_core.vh
index 18a0b4525..e82e3ece4 100644
--- a/fpga/usrp3/top/n3xx/n320_bist_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n320_bist_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-28T12:13:45.942402
+// File generated on: 2022-03-29T22:54:30.568990
// Source: n320_bist_image_core.yml
-// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
+// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
index 0ea15f6c3..89d53c2e9 100644
--- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
+++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:09.950905
+// File generated on: 2022-03-29T22:54:31.762363
// Source: n320_rfnoc_image_core.yml
-// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
+// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
//
`default_nettype none
@@ -60,26 +60,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // radio_ch0
- input wire [ 31:0] radio_rx_data_radio0,
- input wire [ 0:0] radio_rx_stb_radio0,
- output wire [ 0:0] radio_rx_running_radio0,
- output wire [ 31:0] radio_tx_data_radio0,
- input wire [ 0:0] radio_tx_stb_radio0,
- output wire [ 0:0] radio_tx_running_radio0,
- // radio_ch1
- input wire [ 31:0] radio_rx_data_radio1,
- input wire [ 0:0] radio_rx_stb_radio1,
- output wire [ 0:0] radio_rx_running_radio1,
- output wire [ 31:0] radio_tx_data_radio1,
- input wire [ 0:0] radio_tx_stb_radio1,
- output wire [ 0:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -718,7 +718,7 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -729,20 +729,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // radio_iface
- wire [ 31:0] radio0_radio_rx_data;
- wire [ 0:0] radio0_radio_rx_stb;
- wire [ 0:0] radio0_radio_rx_running;
- wire [ 31:0] radio0_radio_tx_data;
- wire [ 0:0] radio0_radio_tx_stb;
- wire [ 0:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -889,7 +891,7 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -900,20 +902,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // radio_iface
- wire [ 31:0] radio1_radio_rx_data;
- wire [ 0:0] radio1_radio_rx_stb;
- wire [ 0:0] radio1_radio_rx_running;
- wire [ 31:0] radio1_radio_tx_data;
- wire [ 0:0] radio1_radio_tx_stb;
- wire [ 0:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -973,7 +977,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
- wire [ 127:0] replay0_m_axi_awaddr;
+ wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -985,8 +989,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
- wire [ 255:0] replay0_m_axi_wdata;
- wire [ 31:0] replay0_m_axi_wstrb;
+ wire [2047:0] replay0_m_axi_wdata;
+ wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -997,7 +1001,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
- wire [ 127:0] replay0_m_axi_araddr;
+ wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1010,7 +1014,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
- wire [ 255:0] replay0_m_axi_rdata;
+ wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
diff --git a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh
index 82cf70236..c5349ad0e 100644
--- a/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/n3xx/n320_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:09.997079
+// File generated on: 2022-03-29T22:54:31.796221
// Source: n320_rfnoc_image_core.yml
-// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
+// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
index dced3c4cb..a0f69c38c 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.v
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:06.967425
+// File generated on: 2022-03-29T22:54:32.588967
// Source: x300_rfnoc_image_core.yml
-// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
+// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
//
`default_nettype none
@@ -61,26 +61,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
- // x300_radio1
- input wire [ 63:0] radio_rx_data_radio1,
- input wire [ 1:0] radio_rx_stb_radio1,
- output wire [ 1:0] radio_rx_running_radio1,
- output wire [ 63:0] radio_tx_data_radio1,
- input wire [ 1:0] radio_tx_stb_radio1,
- output wire [ 1:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -92,8 +92,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -104,7 +104,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -117,7 +117,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -873,7 +873,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -884,20 +884,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1044,7 +1046,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -1055,20 +1057,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // x300_radio
- wire [ 63:0] radio1_radio_rx_data;
- wire [ 1:0] radio1_radio_rx_stb;
- wire [ 1:0] radio1_radio_rx_running;
- wire [ 63:0] radio1_radio_tx_data;
- wire [ 1:0] radio1_radio_tx_stb;
- wire [ 1:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1128,7 +1132,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
- wire [ 127:0] replay0_m_axi_awaddr;
+ wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -1140,8 +1144,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
- wire [ 255:0] replay0_m_axi_wdata;
- wire [ 31:0] replay0_m_axi_wstrb;
+ wire [2047:0] replay0_m_axi_wdata;
+ wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -1152,7 +1156,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
- wire [ 127:0] replay0_m_axi_araddr;
+ wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1165,7 +1169,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
- wire [ 255:0] replay0_m_axi_rdata;
+ wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
diff --git a/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh b/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
index a651f32d1..069a66171 100644
--- a/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x300/x300_rfnoc_image_core.vh
@@ -1,5 +1,5 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:07.013471
+// File generated on: 2022-03-29T22:54:32.623216
// Source: x300_rfnoc_image_core.yml
-// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
+// Source SHA256: 320ab21201cdeaa19e38979dd05012652dec06a89593d17b611d029e6b83d0e5
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
index 45588a7b0..43914f464 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.v
@@ -1,9 +1,9 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
-// Module: rfnoc_image_core (for x300)
+// Module: rfnoc_image_core (for x310)
//
// Description:
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:07.732667
+// File generated on: 2022-03-29T22:54:33.009325
// Source: x310_rfnoc_image_core.yml
-// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
+// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
//
`default_nettype none
@@ -61,26 +61,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
- // time_keeper
+ // time
input wire [ 63:0] radio_time,
- // x300_radio0
- input wire [ 63:0] radio_rx_data_radio0,
- input wire [ 1:0] radio_rx_stb_radio0,
- output wire [ 1:0] radio_rx_running_radio0,
- output wire [ 63:0] radio_tx_data_radio0,
- input wire [ 1:0] radio_tx_stb_radio0,
- output wire [ 1:0] radio_tx_running_radio0,
- // x300_radio1
- input wire [ 63:0] radio_rx_data_radio1,
- input wire [ 1:0] radio_rx_stb_radio1,
- output wire [ 1:0] radio_rx_running_radio1,
- output wire [ 63:0] radio_tx_data_radio1,
- input wire [ 1:0] radio_tx_stb_radio1,
- output wire [ 1:0] radio_tx_running_radio1,
+ // radio0
+ input wire [ 255:0] radio_rx_data_radio0,
+ input wire [ 7:0] radio_rx_stb_radio0,
+ output wire [ 7:0] radio_rx_running_radio0,
+ output wire [ 255:0] radio_tx_data_radio0,
+ input wire [ 7:0] radio_tx_stb_radio0,
+ output wire [ 7:0] radio_tx_running_radio0,
+ // radio1
+ input wire [ 255:0] radio_rx_data_radio1,
+ input wire [ 7:0] radio_rx_stb_radio1,
+ output wire [ 7:0] radio_rx_running_radio1,
+ output wire [ 255:0] radio_tx_data_radio1,
+ input wire [ 7:0] radio_tx_stb_radio1,
+ output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
- output wire [ 127:0] m_axi_awaddr,
+ output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -92,8 +92,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
- output wire [ 255:0] m_axi_wdata,
- output wire [ 31:0] m_axi_wstrb,
+ output wire [2047:0] m_axi_wdata,
+ output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -104,7 +104,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
- output wire [ 127:0] m_axi_araddr,
+ output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -117,7 +117,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
- input wire [ 255:0] m_axi_rdata,
+ input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -873,7 +873,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -884,20 +884,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio0_radio_time;
- // x300_radio
- wire [ 63:0] radio0_radio_rx_data;
- wire [ 1:0] radio0_radio_rx_stb;
- wire [ 1:0] radio0_radio_rx_running;
- wire [ 63:0] radio0_radio_tx_data;
- wire [ 1:0] radio0_radio_tx_stb;
- wire [ 1:0] radio0_radio_tx_running;
+ // radio
+ wire [ 255:0] radio0_radio_rx_data;
+ wire [ 7:0] radio0_radio_rx_stb;
+ wire [ 7:0] radio0_radio_rx_running;
+ wire [ 255:0] radio0_radio_tx_data;
+ wire [ 7:0] radio0_radio_tx_stb;
+ wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1044,7 +1046,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
- // ctrl_port
+ // ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -1055,20 +1057,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
- // time_keeper
+ // time
wire [ 63:0] radio1_radio_time;
- // x300_radio
- wire [ 63:0] radio1_radio_rx_data;
- wire [ 1:0] radio1_radio_rx_stb;
- wire [ 1:0] radio1_radio_rx_running;
- wire [ 63:0] radio1_radio_tx_data;
- wire [ 1:0] radio1_radio_tx_stb;
- wire [ 1:0] radio1_radio_tx_running;
+ // radio
+ wire [ 255:0] radio1_radio_rx_data;
+ wire [ 7:0] radio1_radio_rx_stb;
+ wire [ 7:0] radio1_radio_rx_running;
+ wire [ 255:0] radio1_radio_tx_data;
+ wire [ 7:0] radio1_radio_tx_stb;
+ wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
+ .NIPC (1),
+ .ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1128,7 +1132,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
- wire [ 127:0] replay0_m_axi_awaddr;
+ wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -1140,8 +1144,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
- wire [ 255:0] replay0_m_axi_wdata;
- wire [ 31:0] replay0_m_axi_wstrb;
+ wire [2047:0] replay0_m_axi_wdata;
+ wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -1152,7 +1156,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
- wire [ 127:0] replay0_m_axi_araddr;
+ wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1165,7 +1169,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
- wire [ 255:0] replay0_m_axi_rdata;
+ wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
@@ -1176,8 +1180,8 @@ module rfnoc_image_core #(
.THIS_PORTID (8),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
- .MEM_ADDR_W (30),
.MEM_DATA_W (64),
+ .MEM_ADDR_W (30),
.MTU (MTU)
) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
diff --git a/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh b/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
index 977751101..261b08aec 100644
--- a/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x300/x310_rfnoc_image_core.vh
@@ -1,9 +1,9 @@
//
-// Copyright 2021 Ettus Research, A National Instruments Brand
+// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
-// Header: rfnoc_image_core.vh (for x300)
+// Header: rfnoc_image_core.vh (for x310)
//
// Description:
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2021-05-03T08:51:07.779170
+// File generated on: 2022-03-29T22:54:33.044163
// Source: x310_rfnoc_image_core.yml
-// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
+// Source SHA256: 0b0f8a65bb28bcc85d7f926712074af71994564ef9dea213fbbe2313a3bfd26d
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
index 398ef32dd..968361f4e 100644
--- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-02T14:39:07.260299
-// Source: ./x410_100_rfnoc_image_core.yml
-// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9
+// File generated on: 2022-03-29T22:54:34.224724
+// Source: x410_100_rfnoc_image_core.yml
+// Source SHA256: 9e62fec6fb4c74b9aedd932cb474c3eac35f1455a9947cd72c82d3d3eff505d7
//
`default_nettype none
@@ -569,7 +569,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP4 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
@@ -638,7 +638,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP5 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
@@ -707,7 +707,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP6 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 :
@@ -776,7 +776,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP7 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 :
diff --git a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
index b72dbf932..1502b6bc8 100644
--- a/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_100_rfnoc_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-02T14:39:07.293349
-// Source: ./x410_100_rfnoc_image_core.yml
-// Source SHA256: 0171fb376a68431d88c4d9a1f5b69c5b20ebb0e5b4efacb34173f9349a25e3d9
+// File generated on: 2022-03-29T22:54:34.258722
+// Source: x410_100_rfnoc_image_core.yml
+// Source SHA256: 9e62fec6fb4c74b9aedd932cb474c3eac35f1455a9947cd72c82d3d3eff505d7
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
index 9e71ff039..8b8126bd6 100644
--- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-02T14:39:11.377126
-// Source: ./x410_200_rfnoc_image_core.yml
-// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6
+// File generated on: 2022-03-29T22:54:34.653995
+// Source: x410_200_rfnoc_image_core.yml
+// Source SHA256: 2f39eb00e4449ba15add66b6a3921d729afa21f8c34d609b82ca51d6b4ab8bec
//
`default_nettype none
@@ -569,7 +569,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP4 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP4 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
@@ -638,7 +638,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP5 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP5 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
@@ -707,7 +707,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP6 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP6 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 :
@@ -776,7 +776,7 @@ module rfnoc_image_core #(
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
- localparam REQ_BUFF_SIZE_EP7 = (4096)/(CHDR_W/8);
+ localparam REQ_BUFF_SIZE_EP7 = (16384)/(CHDR_W/8);
localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 :
@@ -1604,20 +1604,6 @@ module rfnoc_image_core #(
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
- assign radio0_radio_rx_data = radio_rx_data_radio0;
- assign radio0_radio_rx_stb = radio_rx_stb_radio0;
- assign radio_rx_running_radio0 = radio0_radio_rx_running;
- assign radio_tx_data_radio0 = radio0_radio_tx_data;
- assign radio0_radio_tx_stb = radio_tx_stb_radio0;
- assign radio_tx_running_radio0 = radio0_radio_tx_running;
-
- assign radio1_radio_rx_data = radio_rx_data_radio1;
- assign radio1_radio_rx_stb = radio_rx_stb_radio1;
- assign radio_rx_running_radio1 = radio1_radio_rx_running;
- assign radio_tx_data_radio1 = radio1_radio_tx_data;
- assign radio1_radio_tx_stb = radio_tx_stb_radio1;
- assign radio_tx_running_radio1 = radio1_radio_tx_running;
-
assign replay0_axi_rst = axi_rst;
assign m_axi_awid = replay0_m_axi_awid;
assign m_axi_awaddr = replay0_m_axi_awaddr;
@@ -1664,6 +1650,20 @@ module rfnoc_image_core #(
assign replay0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = replay0_m_axi_rready;
+ assign radio0_radio_rx_data = radio_rx_data_radio0;
+ assign radio0_radio_rx_stb = radio_rx_stb_radio0;
+ assign radio_rx_running_radio0 = radio0_radio_rx_running;
+ assign radio_tx_data_radio0 = radio0_radio_tx_data;
+ assign radio0_radio_tx_stb = radio_tx_stb_radio0;
+ assign radio_tx_running_radio0 = radio0_radio_tx_running;
+
+ assign radio1_radio_rx_data = radio_rx_data_radio1;
+ assign radio1_radio_rx_stb = radio_rx_stb_radio1;
+ assign radio_rx_running_radio1 = radio1_radio_rx_running;
+ assign radio_tx_data_radio1 = radio1_radio_tx_data;
+ assign radio1_radio_tx_stb = radio_tx_stb_radio1;
+ assign radio_tx_running_radio1 = radio1_radio_tx_running;
+
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
diff --git a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
index 8d9e8af8b..df84f4e22 100644
--- a/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_200_rfnoc_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-02-02T14:39:11.410399
-// Source: ./x410_200_rfnoc_image_core.yml
-// Source SHA256: 57ca44ee7facd8ddcd6a88170463ea9665328e011511c8b5d87684fc78b43bd6
+// File generated on: 2022-03-29T22:54:34.688772
+// Source: x410_200_rfnoc_image_core.yml
+// Source SHA256: 2f39eb00e4449ba15add66b6a3921d729afa21f8c34d609b82ca51d6b4ab8bec
//
`define CHDR_WIDTH 64
diff --git a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v
index d31cc728e..97dd45336 100644
--- a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-14T16:50:52.296419
-// Source: ./x410_400_128_rfnoc_image_core.yml
-// Source SHA256: 78673c977afc0a046ef08c3070fd3600aac7ba8918ce79c698731d693678cd85
+// File generated on: 2022-03-29T22:54:35.478639
+// Source: x410_400_128_rfnoc_image_core.yml
+// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53
//
`default_nettype none
diff --git a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh
index 229eeeefe..81b46ed57 100644
--- a/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_400_128_rfnoc_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-03-14T16:50:52.329591
-// Source: ./x410_400_128_rfnoc_image_core.yml
-// Source SHA256: 78673c977afc0a046ef08c3070fd3600aac7ba8918ce79c698731d693678cd85
+// File generated on: 2022-03-29T22:54:35.513269
+// Source: x410_400_128_rfnoc_image_core.yml
+// Source SHA256: 0e1aea15a9108fa6fbc86d91a7ee9930440a03c66e96bcd86c179ed5b6da5d53
//
`define CHDR_WIDTH 128
diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
index 0d14ecc97..b0fd67b51 100644
--- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
+++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.v
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-01-24T08:37:29.737428
+// File generated on: 2022-03-29T22:54:35.062926
// Source: x410_400_rfnoc_image_core.yml
-// Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e
+// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466
//
`default_nettype none
diff --git a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
index 8b6311c0f..f42109295 100644
--- a/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
+++ b/fpga/usrp3/top/x400/x410_400_rfnoc_image_core.vh
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
-// File generated on: 2022-01-24T08:37:29.769622
+// File generated on: 2022-03-29T22:54:35.096636
// Source: x410_400_rfnoc_image_core.yml
-// Source SHA256: aff421903b98211e4822bd2968fd02c679bf30a215ee65e906d4f9a1d79df71e
+// Source SHA256: 58e375a5b646df42d81e3af066727c562580c7d98df5eb361163e0924463a466
//
`define CHDR_WIDTH 512
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 13:59:28 +0000