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| author | Wade Fife <wade.fife@ettus.com> | 2021-09-10 15:50:13 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-09-13 13:20:37 -0500 |
| commit | ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f (patch) | |
| tree | 8c6f87ad9bab35db39f9135125c7397ea651f37b /fpga/usrp3 | |
| parent | 71aedc922d9cd5348ad4829cf323e569688f660f (diff) | |
| download | uhd-ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f.tar.gz uhd-ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f.tar.bz2 uhd-ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f.zip | |
fpga: n3xx: Update synchronizer constraint
Diffstat (limited to 'fpga/usrp3')
| -rw-r--r-- | fpga/usrp3/top/n3xx/mb_timing.xdc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/fpga/usrp3/top/n3xx/mb_timing.xdc b/fpga/usrp3/top/n3xx/mb_timing.xdc index 6aa3f8132..95265acee 100644 --- a/fpga/usrp3/top/n3xx/mb_timing.xdc +++ b/fpga/usrp3/top/n3xx/mb_timing.xdc @@ -106,6 +106,5 @@ set_max_delay -from $PORT_LIST 50.000 set_min_delay -from $PORT_LIST 0.000 #****************************************************************************** -## Reset Sync False Path -set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D] -set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/C] +## Synchronizer false paths +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] |