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| author | Wade Fife <wade.fife@ettus.com> | 2022-01-12 15:29:14 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-01-12 23:44:38 -0600 |
| commit | 121b6c560cacfb5deacdee664dd1f32cafef7b3d (patch) | |
| tree | 7a05ea5b3a364bd1083d7f00759b06da61475924 /fpga/usrp3 | |
| parent | 2d9a83374760d3b2c36184710e103098566ec3ad (diff) | |
| download | uhd-121b6c560cacfb5deacdee664dd1f32cafef7b3d.tar.gz uhd-121b6c560cacfb5deacdee664dd1f32cafef7b3d.tar.bz2 uhd-121b6c560cacfb5deacdee664dd1f32cafef7b3d.zip | |
fpga: x400: Fix rfnoc_image_core.vh path
Previously, when running rfnoc_image_builder, the rfnoc_image_core.vh
file in the main x400 directory was being used instead of the one
generated by rfnoc_image_builder.
Diffstat (limited to 'fpga/usrp3')
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile.x4xx.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x400/Makefile.x4xx.inc b/fpga/usrp3/top/x400/Makefile.x4xx.inc index 3bcbe38cd..d031d7e83 100644 --- a/fpga/usrp3/top/x400/Makefile.x4xx.inc +++ b/fpga/usrp3/top/x400/Makefile.x4xx.inc @@ -170,7 +170,7 @@ $(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \ # Pass the edge table and image core header files required by RFNoC # to Vivado as Verilog definitions. EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))" -IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)" +IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" ################################################## # Dependency Targets |