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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2021-06-23 11:32:01 -0700 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-01-25 10:18:47 -0700 |
| commit | 87b2cf09301e90dfaf2a6554c424b62e0558e0b1 (patch) | |
| tree | 7327ae0f20ddf6950b38e51bc91edac52aa00154 /fpga/usrp3/top/x400/regmap | |
| parent | 3d045685aba50900f968c48c22759bd76c01bf0a (diff) | |
| download | uhd-87b2cf09301e90dfaf2a6554c424b62e0558e0b1.tar.gz uhd-87b2cf09301e90dfaf2a6554c424b62e0558e0b1.tar.bz2 uhd-87b2cf09301e90dfaf2a6554c424b62e0558e0b1.zip | |
fpga: x400: Connect Radio Blocks to DIO
Diffstat (limited to 'fpga/usrp3/top/x400/regmap')
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh | 15 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh | 4 |
2 files changed, 12 insertions, 7 deletions
diff --git a/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh index 18d442cd1..d9ffa1b38 100644 --- a/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh @@ -11,8 +11,9 @@ // A numerically ordered list of registers and their HDL source files //=============================================================================== - // DB_WINDOW : 0x0 (rfdc_timing_control.v) - // RFDC_TIMING_WINDOW : 0x8000 (rfdc_timing_control.v) + // DB_WINDOW : 0x0 (x4xx_core_common.v) + // RFDC_TIMING_WINDOW : 0x8000 (x4xx_core_common.v) + // DIO_WINDOW : 0xC000 (x4xx_core_common.v) //=============================================================================== // RegTypes @@ -22,10 +23,14 @@ // Register Group RADIO_CTRLPORT_WINDOWS //=============================================================================== - // DB_WINDOW Window (from rfdc_timing_control.v) + // DB_WINDOW Window (from x4xx_core_common.v) localparam DB_WINDOW = 'h0; // Window Offset localparam DB_WINDOW_SIZE = 'h8000; // size in bytes - // RFDC_TIMING_WINDOW Window (from rfdc_timing_control.v) + // RFDC_TIMING_WINDOW Window (from x4xx_core_common.v) localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset - localparam RFDC_TIMING_WINDOW_SIZE = 'h8000; // size in bytes + localparam RFDC_TIMING_WINDOW_SIZE = 'h4000; // size in bytes + + // DIO_WINDOW Window (from x4xx_core_common.v) + localparam DIO_WINDOW = 'hC000; // Window Offset + localparam DIO_WINDOW_SIZE = 'h4000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh index 48401684a..6f34f9e25 100644 --- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -82,10 +82,10 @@ localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD - localparam FPGA_CURRENT_VERSION_MINOR = 'h3; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_CURRENT_VERSION_MINOR = 'h4; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21041616; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21081116; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; |