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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2022-03-02 13:44:35 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-03-04 09:41:24 -0600 |
| commit | 1d7d1226e7576bfad484109afd3aad4e78af111b (patch) | |
| tree | fa80590c2550029cbd2f82fb12c662b0be1df263 /fpga/usrp3/top/x400/regmap | |
| parent | adb352a2ad81d7c6d70ec5880a787b6bab7d19ba (diff) | |
| download | uhd-1d7d1226e7576bfad484109afd3aad4e78af111b.tar.gz uhd-1d7d1226e7576bfad484109afd3aad4e78af111b.tar.bz2 uhd-1d7d1226e7576bfad484109afd3aad4e78af111b.zip | |
fpga: x400: Add SPI Controller Info register
Include a register that contains SPI controller information.
Currently, it only provides the number of slaves addressable
by the SPI engine.
Diffstat (limited to 'fpga/usrp3/top/x400/regmap')
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh | 9 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh index bca2c4da8..21ce45360 100644 --- a/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh @@ -15,6 +15,7 @@ // SPI_TRANSACTION_CONFIG : 0x10 (x4xx_gpio_spi.v) // SPI_TRANSACTION_GO : 0x14 (x4xx_gpio_spi.v) // SPI_STATUS : 0x18 (x4xx_gpio_spi.v) + // CONTROLLER_INFO : 0x1C (x4xx_gpio_spi.v) //=============================================================================== // RegTypes @@ -82,6 +83,14 @@ localparam SPI_READY_MSB = 24; //SPI_STATUS:SPI_READY localparam SPI_READY = 24; //SPI_STATUS:SPI_READY + // CONTROLLER_INFO Register (from x4xx_gpio_spi.v) + localparam CONTROLLER_INFO = 'h1C; // Register Offset + localparam CONTROLLER_INFO_SIZE = 32; // register width in bits + localparam CONTROLLER_INFO_MASK = 32'hF; + localparam SLAVE_COUNT_SIZE = 4; //CONTROLLER_INFO:SLAVE_COUNT + localparam SLAVE_COUNT_MSB = 3; //CONTROLLER_INFO:SLAVE_COUNT + localparam SLAVE_COUNT = 0; //CONTROLLER_INFO:SLAVE_COUNT + // Return the offset of an element of register array SPI_SLAVE_CONFIG function integer SPI_SLAVE_CONFIG (input integer i); SPI_SLAVE_CONFIG = (i * 'h4) + 'h0; diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh index 8928f06f3..84a5dd7b6 100644 --- a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh +++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -82,10 +82,10 @@ localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD - localparam FPGA_CURRENT_VERSION_MINOR = 'h6; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR + localparam FPGA_CURRENT_VERSION_MINOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR - localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22022411; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h22030212; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME // Enumerated type RF_CORE_100M_VERSION localparam RF_CORE_100M_VERSION_SIZE = 7; |