diff options
| author | Wade Fife <wade.fife@ettus.com> | 2021-06-08 19:40:46 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-10 11:56:58 -0500 |
| commit | 6d3765605262016a80f71e36357f749ea35cbe5a (patch) | |
| tree | 7d62d6622befd4132ac1ee085effa1426f7f53e5 /fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh | |
| parent | f706b89e6974e28ce76aadeeb06169becc86acba (diff) | |
| download | uhd-6d3765605262016a80f71e36357f749ea35cbe5a.tar.gz uhd-6d3765605262016a80f71e36357f749ea35cbe5a.tar.bz2 uhd-6d3765605262016a80f71e36357f749ea35cbe5a.zip | |
fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>
Diffstat (limited to 'fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh')
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh new file mode 100644 index 000000000..05e5a48af --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh @@ -0,0 +1,41 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: pl_cpld_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // BASE : 0x0 (cpld_interface.v) + // MB_CPLD : 0x8000 (cpld_interface.v) + // DB0_CPLD : 0x10000 (cpld_interface.v) + // DB1_CPLD : 0x18000 (cpld_interface.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group PL_CPLD_WINDOWS +//=============================================================================== + + // BASE Window (from cpld_interface.v) + localparam BASE = 'h0; // Window Offset + localparam BASE_SIZE = 'h40; // size in bytes + + // MB_CPLD Window (from cpld_interface.v) + localparam MB_CPLD = 'h8000; // Window Offset + localparam MB_CPLD_SIZE = 'h8000; // size in bytes + + // DB0_CPLD Window (from cpld_interface.v) + localparam DB0_CPLD = 'h10000; // Window Offset + localparam DB0_CPLD_SIZE = 'h8000; // size in bytes + + // DB1_CPLD Window (from cpld_interface.v) + localparam DB1_CPLD = 'h18000; // Window Offset + localparam DB1_CPLD_SIZE = 'h8000; // size in bytes |