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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-09 10:13:09 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 0076076467303247c4e62e5824e5bf8ce79cbe66 (patch) | |
| tree | 2fe7e3a987fd38e1e556b71c962d57a97d033f17 /fpga/usrp3/top/x400/ip | |
| parent | 319d8c6411f62a2150b21b38bfe5fd55366ee700 (diff) | |
| download | uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.tar.gz uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.tar.bz2 uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.zip | |
fpga: Update testbenches to work in ModelSim
Diffstat (limited to 'fpga/usrp3/top/x400/ip')
| -rw-r--r-- | fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile index 5ec8b6868..3c57e7402 100644 --- a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile @@ -25,6 +25,7 @@ include $(BASE_DIR)/../lib/fifo/Makefile.srcs #$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \ DESIGN_SRCS = $(abspath \ +$(abspath ../PkgEth100gLbus.sv) \ $(abspath ../eth_100g_axis2lbus.sv) \ $(abspath ../eth_100g_lbus2axis.sv) \ $(FIFO_SRCS) \ @@ -41,7 +42,6 @@ TB_TOP_MODULE ?= lbus_all_tb SIM_TOP = $(TB_TOP_MODULE) SIM_SRCS = \ -$(abspath ../PkgEth100gLbus.sv) \ $(abspath axi_lbus_tb.sv) \ $(abspath lbus_axi_tb.sv) \ $(abspath $(TB_TOP_MODULE).sv) \ |