From 0076076467303247c4e62e5824e5bf8ce79cbe66 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 9 Jun 2021 10:13:09 -0500 Subject: fpga: Update testbenches to work in ModelSim --- fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/top/x400/ip') diff --git a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile index 5ec8b6868..3c57e7402 100644 --- a/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile +++ b/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/Makefile @@ -25,6 +25,7 @@ include $(BASE_DIR)/../lib/fifo/Makefile.srcs #$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \ DESIGN_SRCS = $(abspath \ +$(abspath ../PkgEth100gLbus.sv) \ $(abspath ../eth_100g_axis2lbus.sv) \ $(abspath ../eth_100g_lbus2axis.sv) \ $(FIFO_SRCS) \ @@ -41,7 +42,6 @@ TB_TOP_MODULE ?= lbus_all_tb SIM_TOP = $(TB_TOP_MODULE) SIM_SRCS = \ -$(abspath ../PkgEth100gLbus.sv) \ $(abspath axi_lbus_tb.sv) \ $(abspath lbus_axi_tb.sv) \ $(abspath $(TB_TOP_MODULE).sv) \ -- cgit v1.2.3