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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-08 19:40:46 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-10 11:56:58 -0500 |
| commit | 6d3765605262016a80f71e36357f749ea35cbe5a (patch) | |
| tree | 7d62d6622befd4132ac1ee085effa1426f7f53e5 /fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc | |
| parent | f706b89e6974e28ce76aadeeb06169becc86acba (diff) | |
| download | uhd-6d3765605262016a80f71e36357f749ea35cbe5a.tar.gz uhd-6d3765605262016a80f71e36357f749ea35cbe5a.tar.bz2 uhd-6d3765605262016a80f71e36357f749ea35cbe5a.zip | |
fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>
Diffstat (limited to 'fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc')
| -rw-r--r-- | fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc b/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc new file mode 100644 index 000000000..4df9bcc5f --- /dev/null +++ b/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc @@ -0,0 +1,47 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/viv_ip_builder.mak + +XGE_PCS_PMA_SRCS = \ +$(IP_DIR)/xge_pcs_pma/ten_gige_phy.v \ +$(IP_DIR)/xge_pcs_pma/eth_10g.sv \ +$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) + +IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \ +$(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \ +xge_pcs_pma.v \ +hdl/xxv_ethernet_v3_0_vl_rfs.sv \ +ip_0/hdl/*.v \ +ip_0/sim/*.v \ +xxv_ethernet_v3_0_1/*.v \ +)) + +IP_XGE_PCS_PMA_EXAMPLE_SRCS = \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_common_wrapper.v \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_gt_gtye4_common_wrapper.v \ +$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/gtwizard_ultrascale_v1_7_gtye4_common.v \ + +# Describe the paths for the patch file, the file to be patched, and the +# patched copy of the file. +IP_XGE_FILE_PATCH = $(IP_DIR)/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch +IP_XGE_FILE_TO_PATCH = $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v3_0_1/xge_pcs_pma_wrapper.v +IP_XGE_PATCHED_FILE = $(IP_BUILD_DIR)/xge_pcs_pma_wrapper.v.patched + +IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_PATCHED_FILE) + +IP_XGE_PCS_PMA_OUTS = \ +$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \ +$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.v \ + +$(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS) + +$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS) : $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH) + $(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) + cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_FILE_TO_PATCH).orig + cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_PATCHED_FILE) + patch $(IP_XGE_PATCHED_FILE) $(IP_XGE_FILE_PATCH) + $(call REBUILD_VIVADO_IP_WITH_PATCH,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0,$(call RESOLVE_PATH,$(IP_XGE_PATCHED_FILE)),$(call RESOLVE_PATH,$(IP_XGE_FILE_TO_PATCH))) |