fpga: x400: Add support for X410 motherboard FPGA

Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>

3 files changed, 486 insertions, 0 deletions

diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc
new file mode 100644
index 000000000..31b996bb9
--- /dev/null
+++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/Makefile.inc
@@ -0,0 +1,41 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/viv_ip_builder.mak
+
+IP_AXI_INTERCONNECT_DMA_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \
+axi_interconnect_dma.sv \
+)
+
+IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
+sim/axi_interconnect_dma_bd.v\
+ip/axi_interconnect_dma_bd_xbar_0/sim/axi_interconnect_dma_bd_xbar_0.v\
+ipshared/*/simulation/fifo_generator_vlog_beh.v\
+ipshared/*/hdl/*.v\
+))
+
+IP_AXI_INTERCONNECT_DMA_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_dma_bd/, \
+axi_interconnect_dma_bd.tcl \
+)
+
+IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
+axi_interconnect_dma_bd.tcl \
+)
+
+IP_AXI_INTERCONNECT_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
+axi_interconnect_dma_bd/axi_interconnect_dma_bd.bd \
+)
+
+BD_AXI_INTERCONNECT_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/, \
+axi_interconnect_dma_bd.bd.out \
+axi_interconnect_dma_bd/axi_interconnect_dma_bd_ooc.xdc \
+axi_interconnect_dma_bd/synth/axi_interconnect_dma_bd.v \
+)
+
+
+
+$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) $(BD_AXI_INTERCONNECT_DMA_BD_OUTS) $(IP_AXI_INTERCONNECT_DMA_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_DMA_ORIG_SRCS)
+	$(call BUILD_VIVADO_BDTCL,axi_interconnect_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv
new file mode 100644
index 000000000..9fd2f6589
--- /dev/null
+++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma.sv
@@ -0,0 +1,40 @@
+//
+// Copyright 2021 Ettus Research, A National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_interconnect_dma
+//
+// Description: Wrapper for the Xilinx AXI interconnect block
+//
+
+module axi_interconnect_dma (
+  AxiIf.slave  s_axi_hp_dma [3:0], // Incoming AXI from DMA engines
+  AxiIf.master m_axi_hp            // Outgoing AXI to memory
+);
+
+  // AxiIf_v has no procedural assignments so it can be driven by a port.
+  `include "../../../../lib/axi4_sv/axi.vh"
+  AxiIf_v #(128,49)
+    m_axi_hp_v(.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
+  AxiIf_v #(128,49)
+    s_axi_hp_dma_v[3:0](.clk(m_axi_hp.clk), .rst(m_axi_hp.rst));
+
+  //                    O = I;  (O         ,        I       )
+  always_comb begin `AXI4_ASSIGN(m_axi_hp,          m_axi_hp_v) end
+  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[0], s_axi_hp_dma[0]) end
+  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[1], s_axi_hp_dma[1]) end
+  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[2], s_axi_hp_dma[2]) end
+  always_comb begin `AXI4_ASSIGN(s_axi_hp_dma_v[3], s_axi_hp_dma[3]) end
+
+  axi_interconnect_dma_bd axi_interconnect_dma_bd_i (
+    `AXI4_PORT_ASSIGN_NR(m_axi_hp,      m_axi_hp_v)
+    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma0, s_axi_hp_dma_v[0])
+    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma1, s_axi_hp_dma_v[1])
+    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma2, s_axi_hp_dma_v[2])
+    `AXI4_PORT_ASSIGN_NR(s_axi_hp_dma3, s_axi_hp_dma_v[3])
+    .clk40      (m_axi_hp.clk),
+    .clk40_rstn (!m_axi_hp.rst)
+  );
+
+endmodule
diff --git a/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl
new file mode 100644
index 000000000..43c959ac0
--- /dev/null
+++ b/fpga/usrp3/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl
@@ -0,0 +1,405 @@
+
+################################################################
+# This is a generated script based on design: axi_interconnect_dma_bd
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2019.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source axi_interconnect_dma_bd_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name axi_interconnect_dma_bd
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+"
+
+   set list_ips_missing ""
+   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+  set m_axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_hp ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {49} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {0} \
+   CONFIG.NUM_READ_OUTSTANDING {16} \
+   CONFIG.NUM_WRITE_OUTSTANDING {16} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   ] $m_axi_hp
+
+  set s_axi_hp_dma0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma0 ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {49} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {0} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {0} \
+   CONFIG.MAX_BURST_LENGTH {16} \
+   CONFIG.NUM_READ_OUTSTANDING {8} \
+   CONFIG.NUM_READ_THREADS {4} \
+   CONFIG.NUM_WRITE_OUTSTANDING {8} \
+   CONFIG.NUM_WRITE_THREADS {4} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {0} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $s_axi_hp_dma0
+
+  set s_axi_hp_dma1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma1 ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {49} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {0} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {0} \
+   CONFIG.MAX_BURST_LENGTH {16} \
+   CONFIG.NUM_READ_OUTSTANDING {8} \
+   CONFIG.NUM_READ_THREADS {4} \
+   CONFIG.NUM_WRITE_OUTSTANDING {8} \
+   CONFIG.NUM_WRITE_THREADS {4} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {0} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $s_axi_hp_dma1
+
+  set s_axi_hp_dma2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma2 ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {49} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {0} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {0} \
+   CONFIG.MAX_BURST_LENGTH {16} \
+   CONFIG.NUM_READ_OUTSTANDING {8} \
+   CONFIG.NUM_READ_THREADS {4} \
+   CONFIG.NUM_WRITE_OUTSTANDING {8} \
+   CONFIG.NUM_WRITE_THREADS {4} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {0} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $s_axi_hp_dma2
+
+  set s_axi_hp_dma3 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp_dma3 ]
+  set_property -dict [ list \
+   CONFIG.ADDR_WIDTH {49} \
+   CONFIG.ARUSER_WIDTH {0} \
+   CONFIG.AWUSER_WIDTH {0} \
+   CONFIG.BUSER_WIDTH {0} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.DATA_WIDTH {128} \
+   CONFIG.FREQ_HZ {40000000} \
+   CONFIG.HAS_BRESP {1} \
+   CONFIG.HAS_BURST {1} \
+   CONFIG.HAS_CACHE {1} \
+   CONFIG.HAS_LOCK {1} \
+   CONFIG.HAS_PROT {1} \
+   CONFIG.HAS_QOS {1} \
+   CONFIG.HAS_REGION {0} \
+   CONFIG.HAS_RRESP {1} \
+   CONFIG.HAS_WSTRB {1} \
+   CONFIG.ID_WIDTH {0} \
+   CONFIG.MAX_BURST_LENGTH {16} \
+   CONFIG.NUM_READ_OUTSTANDING {8} \
+   CONFIG.NUM_READ_THREADS {4} \
+   CONFIG.NUM_WRITE_OUTSTANDING {8} \
+   CONFIG.NUM_WRITE_THREADS {4} \
+   CONFIG.PROTOCOL {AXI4} \
+   CONFIG.READ_WRITE_MODE {READ_WRITE} \
+   CONFIG.RUSER_BITS_PER_BYTE {0} \
+   CONFIG.RUSER_WIDTH {0} \
+   CONFIG.SUPPORTS_NARROW_BURST {0} \
+   CONFIG.WUSER_BITS_PER_BYTE {0} \
+   CONFIG.WUSER_WIDTH {0} \
+   ] $s_axi_hp_dma3
+
+
+  # Create ports
+  set clk40 [ create_bd_port -dir I -type clk clk40 ]
+  set_property -dict [ list \
+   CONFIG.ASSOCIATED_BUSIF {s_axi_hp_dma0:s_axi_hp_dma1:s_axi_hp_dma2:s_axi_hp_dma3:m_axi_hp} \
+   CONFIG.ASSOCIATED_RESET {clk40_rstn} \
+   CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
+   CONFIG.FREQ_HZ {40000000} \
+ ] $clk40
+  set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
+
+  # Create instance: axi_interconnect_0, and set properties
+  set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
+  set_property -dict [ list \
+   CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
+   CONFIG.M00_HAS_DATA_FIFO {1} \
+   CONFIG.M00_HAS_REGSLICE {4} \
+   CONFIG.NUM_MI {1} \
+   CONFIG.NUM_SI {4} \
+   CONFIG.S00_HAS_DATA_FIFO {1} \
+   CONFIG.S00_HAS_REGSLICE {4} \
+   CONFIG.S01_ARB_PRIORITY {0} \
+   CONFIG.S01_HAS_DATA_FIFO {1} \
+   CONFIG.S01_HAS_REGSLICE {4} \
+   CONFIG.S02_ARB_PRIORITY {0} \
+   CONFIG.S02_HAS_DATA_FIFO {1} \
+   CONFIG.S02_HAS_REGSLICE {4} \
+   CONFIG.S03_ARB_PRIORITY {0} \
+   CONFIG.S03_HAS_DATA_FIFO {1} \
+   CONFIG.S03_HAS_REGSLICE {4} \
+   CONFIG.STRATEGY {1} \
+ ] $axi_interconnect_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_hp_dma0] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
+  connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_hp] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
+  connect_bd_intf_net -intf_net s_axi_eth1_1 [get_bd_intf_ports s_axi_hp_dma1] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
+  connect_bd_intf_net -intf_net s_axi_eth2_1 [get_bd_intf_ports s_axi_hp_dma2] [get_bd_intf_pins axi_interconnect_0/S02_AXI]
+  connect_bd_intf_net -intf_net s_axi_eth3_1 [get_bd_intf_ports s_axi_hp_dma3] [get_bd_intf_pins axi_interconnect_0/S03_AXI]
+
+  # Create port connections
+  connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins axi_interconnect_0/S03_ACLK]
+  connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN]
+
+  # Create address segments
+  create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
+  create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
+  create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
+  create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+