aboutsummaryrefslogtreecommitdiffstats
path: root/fpga/usrp3/top/x400/doc
diff options
context:
space:
mode:
authorHumberto Jimenez <humberto.jimenez@ni.com>2021-10-27 14:54:46 -0500
committerWade Fife <wade.fife@ettus.com>2021-12-01 10:51:07 -0600
commite1ce4565dbc7336ee806adce7c087bda4fcc77ae (patch)
tree4e3c05beb4b3b5458869034a70028f97fd2b4071 /fpga/usrp3/top/x400/doc
parent37feec8992afaffbea19428a029093ae7f6453e3 (diff)
downloaduhd-e1ce4565dbc7336ee806adce7c087bda4fcc77ae.tar.gz
uhd-e1ce4565dbc7336ee806adce7c087bda4fcc77ae.tar.bz2
uhd-e1ce4565dbc7336ee806adce7c087bda4fcc77ae.zip
fpga: x400: Refactor CPLDs build process
This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes.
Diffstat (limited to 'fpga/usrp3/top/x400/doc')
-rw-r--r--fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm68
1 files changed, 56 insertions, 12 deletions
diff --git a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
index 88c73f60c..8280e353b 100644
--- a/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
+++ b/fpga/usrp3/top/x400/doc/X4XX_FPGA_right.htm
@@ -2338,9 +2338,9 @@ This enumeration is used to create the constants held in the basic registers.
<tr valign="top">
- <td class='value'>553721877</td>
+ <td class='value'>554767892</td>
- <td class='l'>0x21012015</td>
+ <td class='l'>0x21111614</td>
<td class="l" style="text-align: left;">
<p class="name"><a name='CONSTANTS_REGMAP|CONSTANTS_ENUM|CPLD_REVISION'></a>CPLD_REVISION</p>
@@ -14556,10 +14556,12 @@ RFDC timing control interface.
<a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a>
<h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3>
-Those values are the start and end address of the CFM image flash
- sector from Intel's On-Chip Flash IP Generator. Note that the values
- given in the IP generator are byte based where the values of this enum
- are U32 based (divided by 4).
+These values are the start and end address of the CFM image flash
+ sector from Intel's On-Chip Flash IP Generator.
+ Be aware that three different values exist per each of the two
+ supported MAX10 variants: 10M04 and 10M08
+ Note that the values given in the IP generator are byte based where
+ the values of this enum are U32 based (divided by 4).
<table class="enum" border="0" cellspacing="0" cellpadding="0">
<tr class="header" valign="center">
@@ -14583,7 +14585,20 @@ Those values are the start and end address of the CFM image flash
<td class='l'>0x01000</td>
<td class="l" style="text-align: left;">
- <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT</p>
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p>
+
+</td>
+
+</tr>
+
+<tr valign="top">
+
+ <td class='value'>8192</td>
+
+ <td class='l'>0x02000</td>
+
+ <td class="l" style="text-align: left;">
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p>
</td>
@@ -14596,7 +14611,20 @@ Those values are the start and end address of the CFM image flash
<td class='l'>0x09C00</td>
<td class="l" style="text-align: left;">
- <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR'></a>FLASH_PRIMARY_IMAGE_START_ADDR</p>
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p>
+
+</td>
+
+</tr>
+
+<tr valign="top">
+
+ <td class='value'>44032</td>
+
+ <td class='l'>0x0AC00</td>
+
+ <td class="l" style="text-align: left;">
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p>
</td>
@@ -14609,7 +14637,20 @@ Those values are the start and end address of the CFM image flash
<td class='l'>0x127FF</td>
<td class="l" style="text-align: left;">
- <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR'></a>FLASH_PRIMARY_IMAGE_END_ADDR</p>
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p>
+
+</td>
+
+</tr>
+
+<tr valign="top">
+
+ <td class='value'>79871</td>
+
+ <td class='l'>0x137FF</td>
+
+ <td class="l" style="text-align: left;">
+ <p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p>
</td>
@@ -14999,9 +15040,12 @@ Total Offset =</td></tr>
<p>Defines the sector to be erased. Has to be set latest with the
write access which starts the erase operation by strobing
<a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br>
- If the flash is configured to support memory initialization (see
- <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 to 4 have to be erased.
- If the flag is not asserted only sector 4 has to be erased.</p>
+ With 10M04 variants, if the flash is configured to support memory
+ initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2
+ to 4 have to be erased. If the flag is not asserted only sector 4
+ has to be erased.
+ With 10M08 variants, the sectors to be erased are 3 to 5 when
+ using memory initialization or only sector 5 otherwise.</p>
</td>
</tr>