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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2022-06-14 10:12:05 -0500 |
|---|---|---|
| committer | skooNI <60897865+skooNI@users.noreply.github.com> | 2022-07-20 15:57:20 -0500 |
| commit | 303ddf1238ef1d38fb8b25f7e97b2319475299c1 (patch) | |
| tree | ee9aba5aca59ee20dc7b618ab41c4cc7ba18ba40 /fpga/usrp3/top/x400/cpld/mb_cpld.sdc | |
| parent | 32786c63930bc532bca1f25ab8d3404b5773edfd (diff) | |
| download | uhd-303ddf1238ef1d38fb8b25f7e97b2319475299c1.tar.gz uhd-303ddf1238ef1d38fb8b25f7e97b2319475299c1.tar.bz2 uhd-303ddf1238ef1d38fb8b25f7e97b2319475299c1.zip | |
fpga: x400: zbx: Add support for XO3 CPLD variant.
The main changes included are:
- Variant-dependent pin-out instantiation.
- Update clocking scheme in top level file
to include XO3 PLL
- Add ability to shift outgoing data for
the GPIO communication interface with
the X410 FPGA.
- Include project files required to build
the XO3 variant of the ZBX CPLD.
- Add build flow for Lattice Diamond designs.
- Add ability to build XO3 variant of ZBX CPLD.
Diffstat (limited to 'fpga/usrp3/top/x400/cpld/mb_cpld.sdc')
0 files changed, 0 insertions, 0 deletions