fpga: x400: Refactor CPLDs build process

This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.

6 files changed, 55 insertions, 1 deletions

diff --git a/fpga/usrp3/top/x400/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc
new file mode 100644
index 000000000..1d238d83c
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(IP_DIR)/on_chip_flash/Makefile.inc
+include $(IP_DIR)/clkctrl/Makefile.inc
+
+IP_SRCS = \
+$(IP_ON_CHIP_FLASH_SRCS) \
+$(IP_CLKCTRL_SRCS)
+
+
+IP_OUTPUTS = \
+$(IP_ON_CHIP_FLASH_OUTS) \
+$(IP_CLKCTRL_OUTS)
+
+
+ip: $(IP_OUTPUTS)
+
+.PHONY: ip
diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore
index 9776d9b81..87dce88a7 100644
--- a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore
+++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore
@@ -1,3 +1,3 @@
 # generate files
 clkctrl/
-clkctrl.sopcinfo
\ No newline at end of file
+clkctrl.sopcinfo
diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc
new file mode 100644
index 000000000..2015c6976
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/quartus_ip_builder.mak
+
+IP_CLKCTRL_SRCS = \
+$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys
+
+IP_CLKCTRL_OUTS = \
+$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo
+
+$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys
+	$(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore
index 585bc126d..585bc126d 100644
--- a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore
diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc
new file mode 100644
index 000000000..fcd8528e6
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+
+include $(TOOLS_DIR)/make/quartus_ip_builder.mak
+
+IP_ON_CHIP_FLASH_SRCS = \
+$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys
+
+IP_ON_CHIP_FLASH_OUTS = \
+$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo
+
+$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys
+	$(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys
index 4cbe8726a..4cbe8726a 100644
--- a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys
+++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys