diff options
| author | Ashish Chaudhari <ashish@ettus.com> | 2014-08-20 09:06:32 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-08-20 09:06:32 -0700 |
| commit | 72eae0503393966dfb2b961835ad1f9c5e5265e7 (patch) | |
| tree | 60db7af4b572f280f3017b8ba3a5f39657c58816 /fpga/usrp3/top/x300/timing.ucf | |
| parent | 505c1d84fa7c53c0c640fab73b88c164671c7b91 (diff) | |
| parent | d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82 (diff) | |
| download | uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.tar.gz uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.tar.bz2 uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.zip | |
Merge branch 'master' into ashish/cat_refactor_phase2
Diffstat (limited to 'fpga/usrp3/top/x300/timing.ucf')
| -rw-r--r-- | fpga/usrp3/top/x300/timing.ucf | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf index a84a92a63..b638b2c99 100644 --- a/fpga/usrp3/top/x300/timing.ucf +++ b/fpga/usrp3/top/x300/timing.ucf @@ -34,3 +34,8 @@ TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_gr TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG; TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG; +# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain +# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent, +# lock the locations of the MMCM and BUFG to generate radio_clk. +INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0; +INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8;
\ No newline at end of file |