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authorWade Fife <wade.fife@ettus.com>2021-06-09 10:13:09 -0500
committerWade Fife <wade.fife@ettus.com>2021-06-17 08:16:59 -0500
commit0076076467303247c4e62e5824e5bf8ce79cbe66 (patch)
tree2fe7e3a987fd38e1e556b71c962d57a97d033f17 /fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile
parent319d8c6411f62a2150b21b38bfe5fd55366ee700 (diff)
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fpga: Update testbenches to work in ModelSim
Diffstat (limited to 'fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile')
-rw-r--r--fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile24
1 files changed, 21 insertions, 3 deletions
diff --git a/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile
index 8e75817b1..6a57a5510 100644
--- a/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile
+++ b/fpga/usrp3/top/x300/sim/dram_fifo_bist/Makefile
@@ -53,15 +53,33 @@ $(IP_AXI4_BRAM_SRCS) \
)
#-------------------------------------------------
+# ModelSim Specific
+#-------------------------------------------------
+
+MODELSIM_IP_SRCS = $(wildcard $(abspath \
+$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
+$(IP_BUILD_DIR)/axi4_dualport_sram/sim/axi4_dualport_sram.v \
+$(VIVADO_PATH)/data/verilog/src/glbl.v \
+))
+
+MODELSIM_LIBS += \
+fifo_generator_v13_2_4 \
+blk_mem_gen_v8_4_3 \
+
+modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
+
+MODELSIM_ARGS += glbl -t 1fs
+
+#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
-# Define only one toplevel module
+# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
-SIM_SRCS = \
+SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
-$(IP_DDR3_32BIT_SIM_OUTS)
+$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile