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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-09 10:13:09 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 0076076467303247c4e62e5824e5bf8ce79cbe66 (patch) | |
| tree | 2fe7e3a987fd38e1e556b71c962d57a97d033f17 /fpga/usrp3/top/x300/sim/aurora_loopback | |
| parent | 319d8c6411f62a2150b21b38bfe5fd55366ee700 (diff) | |
| download | uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.tar.gz uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.tar.bz2 uhd-0076076467303247c4e62e5824e5bf8ce79cbe66.zip | |
fpga: Update testbenches to work in ModelSim
Diffstat (limited to 'fpga/usrp3/top/x300/sim/aurora_loopback')
| -rw-r--r-- | fpga/usrp3/top/x300/sim/aurora_loopback/Makefile | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile index eb135ef4e..b7621c4a3 100644 --- a/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile +++ b/fpga/usrp3/top/x300/sim/aurora_loopback/Makefile @@ -51,6 +51,30 @@ $(AURORA_PHY_SRCS) \ ) #------------------------------------------------- +# ModelSim Specific +#------------------------------------------------- + +MODELSIM_IP_SRCS = $(wildcard $(abspath \ +$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \ +$(IP_BUILD_DIR)/axi64_4k_2clk_fifo/sim/axi64_4k_2clk_fifo.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma_core.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/src/*.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/*.v \ +$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/gt/*.v \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ +)) + +MODELSIM_LIBS += \ +unisims_ver \ +unimacro_ver \ +secureip \ +fifo_generator_v13_2_4 \ + + +MODELSIM_ARGS += glbl -t 1fs + +#------------------------------------------------- # Testbench Specific #------------------------------------------------- include $(BASE_DIR)/../sim/general/Makefile.srcs @@ -66,7 +90,8 @@ SIM_SRCS = \ $(abspath aurora_loopback_tb.sv) \ $(SIM_GENERAL_SRCS) \ $(SIM_CONTROL_SRCS) \ -$(SIM_AXI_SRCS) +$(SIM_AXI_SRCS) \ +$(MODELSIM_IP_SRCS) \ #------------------------------------------------- # Bottom-of-Makefile |