Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 106 insertions, 0 deletions

diff --git a/fpga/usrp3/top/x300/gen_ddrlvds.v b/fpga/usrp3/top/x300/gen_ddrlvds.v
new file mode 100644
index 000000000..5773b296c
--- /dev/null
+++ b/fpga/usrp3/top/x300/gen_ddrlvds.v
@@ -0,0 +1,106 @@
+
+
+module gen_ddrlvds
+  (
+   // 1X Radio Clock
+   input tx_clk_1x,
+   // 2X Radio clock
+   input tx_clk_2x,
+   // Clk to drive DCI ODDR. This is a phase shifted version of
+   // tx_clk_2x. The phase shift is to center the DCI edge in the
+   // valid window of the data in the DAC.
+   input tx_dci_clk,
+   // Reset signal synchronous to radio clock
+   input reset,
+   // Source synchronous differential clocks to DAC
+   output tx_clk_2x_p, 
+   output tx_clk_2x_n,
+   // Differential frame sync to DAC
+   output tx_frame_p, 
+   output tx_frame_n,
+   // Differential byte wide data to DAC.
+   // Alternates I[15:8],I[7:0],Q[15:8],Q[7:0]
+   output [7:0] tx_d_p, 
+   output [7:0] tx_d_n,
+   // Input data
+   input [15:0] i, 
+   input [15:0] q,
+   // Rising edge sampled on sync_dacs triggers frame sync sequence
+   input sync_dacs
+   );
+
+   reg [15:0] 	i_reg, q_reg;
+   reg [15:0] 	i_2x, q_2x;
+   reg 		rising_edge;
+   wire [15:0] 	i_and_q_2x;
+   reg 		sync_2x;
+   
+   genvar 	z;
+   wire [7:0] 	tx_int;
+   wire 	tx_clk_2x_int;
+   wire 	tx_frame_int;
+
+   // Keep constraint to ensure these signals are not resource shared which can cause timing failures
+   (* keep = "true" *) reg phase, phase_2x, sync_dacs_reg;
+
+   wire phase_eq_phase2x = (phase == phase_2x);
+
+   always @(posedge tx_clk_1x)
+     if (reset)
+       phase <= 1'b0;
+     else
+       phase <= ~phase;
+
+
+   //
+   // Pipeline input data so that 1x to 2x clock domain jump includes no logic external to this module.
+   //
+   always @(posedge tx_clk_1x) 
+     begin
+	i_reg <= i;
+	q_reg <= q;
+	sync_dacs_reg <= sync_dacs;
+     end  
+
+   always @(posedge tx_clk_2x)
+     begin
+	// Move 1x data to 2x domain, mostly just to add pipeline regs
+	// for timing closure.
+	i_2x <= i_reg;
+	q_2x <= q_reg;
+	// Sample phase to determine when 1x clock edges occur.
+	// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
+	// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
+	// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
+	sync_2x <=  (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
+	rising_edge <= (phase_eq_phase2x && ~sync_2x);
+	phase_2x <= phase;
+     end
+
+   // Interleave I and Q as SDR signals
+   assign i_and_q_2x = rising_edge ? q_2x : i_2x;
+   
+   generate	
+      for(z = 0; z < 8; z = z + 1)
+	begin : gen_pins
+	   OBUFDS obufds (.I(tx_int[z]), .O(tx_d_p[z]), .OB(tx_d_n[z]));
+	   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr
+	     (.Q(tx_int[z]), .C(tx_clk_2x),
+	      .CE(1'b1), .D1(i_and_q_2x[z+8]), .D2(i_and_q_2x[z]), .S(1'b0), .R(1'b0));
+	end
+   endgenerate
+
+   // Generate framing signal to identify I and Q
+   OBUFDS obufds_frame (.I(tx_frame_int), .O(tx_frame_p), .OB(tx_frame_n));
+   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_frame
+     (.Q(tx_frame_int), .C(tx_clk_2x),
+      .CE(1'b1), .D1(~rising_edge), .D2(~rising_edge), .S(1'b0), .R(1'b0));
+
+   // Source synchronous clk
+   OBUFDS obufds_clk (.I(tx_clk_2x_int), .O(tx_clk_2x_p), .OB(tx_clk_2x_n));
+   ODDR #(.DDR_CLK_EDGE("SAME_EDGE")) oddr_clk
+     (.Q(tx_clk_2x_int), .C(tx_dci_clk),
+      .CE(1'b1), .D1(1'b1), .D2(1'b0), .S(1'b0), .R(1'b0));
+
+endmodule // gen_ddrlvds
+