Pushing the bulk of UHD-3.7.0 code.

44 files changed, 3700 insertions, 0 deletions

diff --git a/fpga/usrp3/top/x300/coregen/bootram/blk_mem_gen_v7_3_readme.txt b/fpga/usrp3/top/x300/coregen/bootram/blk_mem_gen_v7_3_readme.txt
new file mode 100644
index 000000000..80625fa3d
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/blk_mem_gen_v7_3_readme.txt
@@ -0,0 +1,213 @@
+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 7.3 Rev 1
+                Release: ISE 14.4 / Vivado 2012.4
+                Release Date: October 16, 2012
+
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURES HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 
+solution. For the latest core updates, see the product page at:
+ 
+ http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+  Zynq-7000 devices
+  All Virtex-6 devices
+  All Spartan-6 devices
+  All Virtex-5 devices
+  All Spartan-3 devices
+  All Virtex-4 devices
+  
+
+  2.2 Vivado 
+  All 7 Series devices
+  Zynq-7000 devices
+
+................................................................................
+
+3. NEW FEATURES HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.3: 
+  
+  4.1 ISE 
+  
+
+  4.2 Vivado
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    The following are known issues for v7.3 of this core at time of release:
+  
+    1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+  
+    3. Core does not generate for large memories. Depending on the
+       machine the ISE CORE Generator software runs on, the maximum size of the memory that
+       can be generated will vary.  For example, a Dual Pentium-4 server 
+       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+    
+
+  5.2 Vivado 
+
+    The following are known issues for v7.3 of this core at time of release:
+     
+  The most recent information, including known issues, workarounds, and resolutions for 
+  this version is provided in the IP Release Notes User Guide located at
+    
+         www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/16/2012  Xilinx, Inc.  7.3 Rev 1    ISE 14.4 and Vivado 2012.4 support;
+10/16/2012  Xilinx, Inc.  7.3          ISE 14.3 and Vivado 2012.3 support;
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support 
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
diff --git a/fpga/usrp3/top/x300/coregen/bootram/doc/blk_mem_gen_v7_3_vinfo.html b/fpga/usrp3/top/x300/coregen/bootram/doc/blk_mem_gen_v7_3_vinfo.html
new file mode 100644
index 000000000..01edd023b
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/doc/blk_mem_gen_v7_3_vinfo.html
@@ -0,0 +1,224 @@
+<HTML>
+<HEAD>
+<TITLE>blk_mem_gen_v7_3_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 7.3 Rev 1
+                Release: ISE 14.4 / Vivado 2012.4
+                Release Date: October 16, 2012
+
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURES HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 
+solution. For the latest core updates, see the product page at:
+ 
+ <A HREF="http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm">www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm</A>
+
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+  Zynq-7000 devices
+  All Virtex-6 devices
+  All Spartan-6 devices
+  All Virtex-5 devices
+  All Spartan-3 devices
+  All Virtex-4 devices
+  
+
+  2.2 Vivado 
+  All 7 Series devices
+  Zynq-7000 devices
+
+................................................................................
+
+3. NEW FEATURES HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.3: 
+  
+  4.1 ISE 
+  
+
+  4.2 Vivado
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    The following are known issues for v7.3 of this core at time of release:
+  
+    1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+  
+    3. Core does not generate for large memories. Depending on the
+       machine the ISE CORE Generator software runs on, the maximum size of the memory that
+       can be generated will vary.  For example, a Dual Pentium-4 server 
+       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+    
+
+  5.2 Vivado 
+
+    The following are known issues for v7.3 of this core at time of release:
+     
+  The most recent information, including known issues, workarounds, and resolutions for 
+  this version is provided in the IP Release Notes User Guide located at
+    
+         <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/16/2012  Xilinx, Inc.  7.3 Rev 1    ISE 14.4 and Vivado 2012.4 support;
+10/16/2012  Xilinx, Inc.  7.3          ISE 14.3 and Vivado 2012.3 support;
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support 
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+</FONT>
+</PRE>
+</BODY>
+</HTML>
diff --git a/fpga/usrp3/top/x300/coregen/bootram/doc/pg058-blk-mem-gen.pdf b/fpga/usrp3/top/x300/coregen/bootram/doc/pg058-blk-mem-gen.pdf
new file mode 100644
index 000000000..967bd7cdd
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/doc/pg058-blk-mem-gen.pdf
diff --git a/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.ucf b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.ucf
new file mode 100755
index 000000000..9b76567eb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.ucf
@@ -0,0 +1,57 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Tx Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+NET "CLKA"  TNM_NET     = "CLKA";
+
+TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
+
+################################################################################
diff --git a/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.vhd b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.vhd
new file mode 100755
index 000000000..661fe5846
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.vhd
@@ -0,0 +1,167 @@
+ 
+ 
+ 
+
+ 
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level core wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bootram_exdes.vhd
+--
+-- Description:
+--   This is the actual BMG core wrapper.
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY bootram_exdes IS
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+  
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    CLKA       : IN STD_LOGIC
+
+
+  );
+
+END bootram_exdes;
+
+
+ARCHITECTURE xilinx OF bootram_exdes IS
+
+  COMPONENT BUFG IS
+  PORT (
+     I      : IN STD_ULOGIC;
+     O      : OUT STD_ULOGIC
+  );
+  END COMPONENT;
+
+  COMPONENT bootram IS
+  PORT (
+      --Port A
+    ENA        : IN STD_LOGIC;  --opt port
+  
+    WEA        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+  
+    DOUTA      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    CLKA       : IN STD_LOGIC
+
+
+
+  );
+  END COMPONENT;
+
+  SIGNAL CLKA_buf     : STD_LOGIC;
+  SIGNAL CLKB_buf     : STD_LOGIC;
+  SIGNAL S_ACLK_buf   : STD_LOGIC;
+
+BEGIN
+
+  bufg_A : BUFG
+    PORT MAP (
+     I => CLKA,
+     O => CLKA_buf
+     );
+
+
+
+  bmg0 : bootram
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+  
+      DOUTA      => DOUTA,
+
+      CLKA       => CLKA_buf
+
+
+    );
+
+END xilinx;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.xdc b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.xdc
new file mode 100755
index 000000000..3dc2b0fbb
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_exdes.xdc
@@ -0,0 +1,54 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
+################################################################################
diff --git a/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_prod.vhd b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_prod.vhd
new file mode 100755
index 000000000..c548a676a
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/example_design/bootram_prod.vhd
@@ -0,0 +1,271 @@
+ 
+ 
+ 
+
+ 
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7.1 Core - Top-level wrapper
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--------------------------------------------------------------------------------
+--
+-- Filename: bootram_prod.vhd
+--
+-- Description:
+--   This is the top-level BMG wrapper (over BMG core).
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: August 31, 2005 - First Release
+--------------------------------------------------------------------------------
+--
+-- Configured Core Parameter Values:
+-- (Refer to the SIM Parameters table in the datasheet for more information on
+-- the these parameters.)
+--    C_FAMILY                    :  kintex7 
+--    C_XDEVICEFAMILY             :  kintex7 
+--    C_INTERFACE_TYPE            :  0 
+--    C_ENABLE_32BIT_ADDRESS      :  0 
+--    C_AXI_TYPE                  :  1 
+--    C_AXI_SLAVE_TYPE            :  0 
+--    C_AXI_ID_WIDTH              :  4 
+--    C_MEM_TYPE                  :  0 
+--    C_BYTE_SIZE                 :  8 
+--    C_ALGORITHM                 :  1 
+--    C_PRIM_TYPE                 :  1 
+--    C_LOAD_INIT_FILE            :  1 
+--    C_INIT_FILE_NAME            :  bootram.mif 
+--    C_USE_DEFAULT_DATA          :  1 
+--    C_DEFAULT_DATA              :  0 
+--    C_RST_TYPE                  :  SYNC 
+--    C_HAS_RSTA                  :  0 
+--    C_RST_PRIORITY_A            :  CE 
+--    C_RSTRAM_A                  :  0 
+--    C_INITA_VAL                 :  0 
+--    C_HAS_ENA                   :  1 
+--    C_HAS_REGCEA                :  0 
+--    C_USE_BYTE_WEA              :  1 
+--    C_WEA_WIDTH                 :  4 
+--    C_WRITE_MODE_A              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_A             :  32 
+--    C_READ_WIDTH_A              :  32 
+--    C_WRITE_DEPTH_A             :  8192 
+--    C_READ_DEPTH_A              :  8192 
+--    C_ADDRA_WIDTH               :  13 
+--    C_HAS_RSTB                  :  0 
+--    C_RST_PRIORITY_B            :  CE 
+--    C_RSTRAM_B                  :  0 
+--    C_INITB_VAL                 :  0 
+--    C_HAS_ENB                   :  0 
+--    C_HAS_REGCEB                :  0 
+--    C_USE_BYTE_WEB              :  1 
+--    C_WEB_WIDTH                 :  4 
+--    C_WRITE_MODE_B              :  WRITE_FIRST 
+--    C_WRITE_WIDTH_B             :  32 
+--    C_READ_WIDTH_B              :  32 
+--    C_WRITE_DEPTH_B             :  8192 
+--    C_READ_DEPTH_B              :  8192 
+--    C_ADDRB_WIDTH               :  13 
+--    C_HAS_MEM_OUTPUT_REGS_A     :  0 
+--    C_HAS_MEM_OUTPUT_REGS_B     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_A     :  0 
+--    C_HAS_MUX_OUTPUT_REGS_B     :  0 
+--    C_HAS_SOFTECC_INPUT_REGS_A  :  0 
+--    C_HAS_SOFTECC_OUTPUT_REGS_B :  0 
+--    C_MUX_PIPELINE_STAGES       :  0 
+--    C_USE_ECC                   :  0 
+--    C_USE_SOFTECC               :  0 
+--    C_HAS_INJECTERR             :  0 
+--    C_SIM_COLLISION_CHECK       :  ALL 
+--    C_COMMON_CLK                :  0 
+--    C_DISABLE_WARN_BHV_COLL     :  0 
+--    C_DISABLE_WARN_BHV_RANGE    :  0 
+
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY UNISIM;
+USE UNISIM.VCOMPONENTS.ALL;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+ENTITY bootram_prod IS
+  PORT (
+    --Port A
+    CLKA       : IN STD_LOGIC;
+    RSTA       : IN STD_LOGIC;  --opt port
+    ENA        : IN STD_LOGIC;  --optional port
+    REGCEA     : IN STD_LOGIC;  --optional port
+    WEA        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINA       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTA      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    --Port B
+    CLKB       : IN STD_LOGIC;
+    RSTB       : IN STD_LOGIC;  --opt port
+    ENB        : IN STD_LOGIC;  --optional port
+    REGCEB     : IN STD_LOGIC;  --optional port
+    WEB        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRB      : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINB       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTB      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    --ECC
+    INJECTSBITERR  : IN STD_LOGIC; --optional port
+    INJECTDBITERR  : IN STD_LOGIC; --optional port
+    SBITERR        : OUT STD_LOGIC; --optional port
+    DBITERR        : OUT STD_LOGIC; --optional port
+    RDADDRECC      : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
+ -- AXI BMG Input and Output Port Declarations
+
+    -- AXI Global Signals
+    S_ACLK                         : IN  STD_LOGIC;
+    S_AXI_AWID                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+    S_AXI_AWADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_AWLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_AWSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_AWBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_AWVALID                  : IN  STD_LOGIC;
+    S_AXI_AWREADY                  : OUT STD_LOGIC;
+    S_AXI_WDATA                    : IN  STD_LOGIC_VECTOR(31  DOWNTO 0);
+    S_AXI_WSTRB                    : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_WLAST                    : IN  STD_LOGIC;
+    S_AXI_WVALID                   : IN  STD_LOGIC;
+    S_AXI_WREADY                   : OUT STD_LOGIC;
+    S_AXI_BID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_BRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_BVALID                   : OUT STD_LOGIC;
+    S_AXI_BREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Slave Read (Write side)
+    S_AXI_ARID                     : IN  STD_LOGIC_VECTOR(3  DOWNTO 0);
+    S_AXI_ARADDR                   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    S_AXI_ARLEN                    : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    S_AXI_ARSIZE                   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
+    S_AXI_ARBURST                  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_ARVALID                  : IN  STD_LOGIC;
+    S_AXI_ARREADY                  : OUT STD_LOGIC;
+    S_AXI_RID                      : OUT STD_LOGIC_VECTOR(3  DOWNTO 0):= (OTHERS => '0');
+    S_AXI_RDATA                    : OUT STD_LOGIC_VECTOR(31  DOWNTO 0);
+    S_AXI_RRESP                    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    S_AXI_RLAST                    : OUT STD_LOGIC;
+    S_AXI_RVALID                   : OUT STD_LOGIC;
+    S_AXI_RREADY                   : IN  STD_LOGIC;
+
+    -- AXI Full/Lite Sideband Signals
+    S_AXI_INJECTSBITERR            : IN  STD_LOGIC;
+    S_AXI_INJECTDBITERR            : IN  STD_LOGIC;
+    S_AXI_SBITERR                  : OUT STD_LOGIC;
+    S_AXI_DBITERR                  : OUT STD_LOGIC;
+    S_AXI_RDADDRECC                : OUT STD_LOGIC_VECTOR(12  DOWNTO 0);
+    S_ARESETN                      : IN  STD_LOGIC
+
+
+  );
+
+END bootram_prod;
+
+
+ARCHITECTURE xilinx OF bootram_prod IS
+
+  COMPONENT bootram_exdes IS
+  PORT (
+      --Port A
+    ENA            : IN STD_LOGIC;  --opt port
+  
+    WEA            : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+  
+    DINA           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+  
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    CLKA       : IN STD_LOGIC
+
+
+
+
+  );
+  END COMPONENT;
+
+BEGIN
+
+  bmg0 : bootram_exdes
+    PORT MAP (
+      --Port A
+      ENA        => ENA,
+  
+      WEA        => WEA,
+      ADDRA      => ADDRA,
+  
+      DINA       => DINA,
+  
+      DOUTA      => DOUTA,
+
+      CLKA       => CLKA
+
+
+
+      );
+END xilinx;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/implement.bat b/fpga/usrp3/top/x300/coregen/bootram/implement/implement.bat
new file mode 100755
index 000000000..379188991
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/implement.bat
@@ -0,0 +1,49 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+rem Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+rem Synthesize the VHDL Wrapper Files
+
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+copy bootram_exdes.ngc .\results\
+
+
+rem Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+copy ..\..\bootram.ngc results\
+
+
+rem  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\bootram_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
+
+echo 'Running map'
+map bootram_exdes -o mapped.ncd  -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/implement.sh b/fpga/usrp3/top/x300/coregen/bootram/implement/implement.sh
new file mode 100755
index 000000000..c8b819bb9
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/implement.sh
@@ -0,0 +1,49 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+#!/bin/sh
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+#Synthesize the Wrapper Files
+
+echo 'Synthesizing example design with XST';
+xst -ifn xst.scr
+cp bootram_exdes.ngc ./results/
+
+
+# Copy the netlist generated by Coregen
+echo 'Copying files from the netlist directory to the results directory'
+cp ../../bootram.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/bootram_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
+
+echo 'Running map'
+map bootram_exdes -o mapped.ncd -pr i
+
+echo 'Running par'
+par mapped.ncd routed.ncd
+
+echo 'Running trce'
+trce -e 10 routed.ncd mapped.pcf -o routed
+
+echo 'Running design through bitgen'
+bitgen -w routed -g UnconstrainedPins:Allow
+
+echo 'Running netgen to create gate level Verilog model'
+netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.bat b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.bat
new file mode 100755
index 000000000..d5940e3d8
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.bat
@@ -0,0 +1,55 @@
+#!/bin/sh
+rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+rem 
+rem This file contains confidential and proprietary information
+rem of Xilinx, Inc. and is protected under U.S. and
+rem international copyright and other intellectual property
+rem laws.
+rem 
+rem DISCLAIMER
+rem This disclaimer is not a license and does not grant any
+rem rights to the materials distributed herewith. Except as
+rem otherwise provided in a valid license issued to you by
+rem Xilinx, and to the maximum extent permitted by applicable
+rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+rem (2) Xilinx shall not be liable (whether in contract or tort,
+rem including negligence, or under any other theory of
+rem liability) for any loss or damage of any kind or nature
+rem related to, arising under or in connection with these
+rem materials, including for any direct, or any indirect,
+rem special, incidental, or consequential loss or damage
+rem (including loss of data, profits, goodwill, or any type of
+rem loss or damage suffered as a result of any action brought
+rem by a third party) even if such damage or loss was
+rem reasonably foreseeable or Xilinx had been advised of the
+rem possibility of the same.
+rem 
+rem CRITICAL APPLICATIONS
+rem Xilinx products are not designed or intended to be fail-
+rem safe, or for use in any application requiring fail-safe
+rem performance, such as life-support or safety devices or
+rem systems, Class III medical devices, nuclear facilities,
+rem applications related to the deployment of airbags, or any
+rem other applications that could lead to death, personal
+rem injury, or severe property or environmental damage
+rem (individually and collectively, "Critical
+rem Applications"). Customer assumes the sole risk and
+rem liability of any use of Xilinx products in Critical
+rem Applications, subject only to applicable laws and
+rem regulations governing limitations on product liability.
+rem 
+rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+rem PART OF THIS FILE AT ALL TIMES.
+
+rem -----------------------------------------------------------------------------
+rem  Script to synthesize and implement the Coregen FIFO Generator
+rem -----------------------------------------------------------------------------
+rmdir /S /Q results
+mkdir results
+cd results
+copy ..\..\..\bootram.ngc .
+planAhead -mode batch -source ..\planAhead_ise.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.sh b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.sh
new file mode 100755
index 000000000..37ba4786d
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.sh
@@ -0,0 +1,55 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#-----------------------------------------------------------------------------
+#  Script to synthesize and implement the Coregen FIFO Generator
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+cp ../../../bootram.ngc .
+planAhead -mode batch -source ../planAhead_ise.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.tcl b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.tcl
new file mode 100755
index 000000000..f821174f8
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/planAhead_ise.tcl
@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc7k410tffg900-2
+set projName bootram
+set design bootram
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module bootram_exdes
+add_files -norecurse {../../example_design/bootram_exdes.vhd}
+add_files -norecurse {./bootram.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/bootram_exdes.xdc}
+set_property top bootram_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module bootram_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module bootram_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/xst.prj b/fpga/usrp3/top/x300/coregen/bootram/implement/xst.prj
new file mode 100755
index 000000000..3ba90883a
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/xst.prj
@@ -0,0 +1 @@
+work ../example_design/bootram_exdes.vhd
diff --git a/fpga/usrp3/top/x300/coregen/bootram/implement/xst.scr b/fpga/usrp3/top/x300/coregen/bootram/implement/xst.scr
new file mode 100755
index 000000000..62a57ab34
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/implement/xst.scr
@@ -0,0 +1,13 @@
+run
+-ifmt VHDL
+-ent bootram_exdes
+-p xc7k410t-ffg900-2
+-ifn xst.prj
+-write_timing_constraints No
+-iobuf YES
+-max_fanout 100
+-ofn bootram_exdes 
+-ofmt NGC
+-bus_delimiter ()
+-hierarchy_separator /
+-case Maintain
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/addr_gen.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/addr_gen.vhd
new file mode 100755
index 000000000..62706ca13
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/addr_gen.vhd
@@ -0,0 +1,117 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Address Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: addr_gen.vhd
+--
+-- Description:
+--   Address Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY ADDR_GEN IS
+  GENERIC ( C_MAX_DEPTH : INTEGER :=  1024 ;
+            RST_VALUE  : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
+            RST_INC  : INTEGER := 0);
+  PORT (
+        CLK         : IN STD_LOGIC;
+        RST         : IN STD_LOGIC;
+        EN          : IN STD_LOGIC;
+        LOAD        :IN STD_LOGIC;
+        LOAD_VALUE  : IN STD_LOGIC_VECTOR (31 DOWNTO 0)  := (OTHERS => '0');
+        ADDR_OUT    : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END ADDR_GEN;
+
+ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
+   SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
+BEGIN
+   ADDR_OUT <= ADDR_TEMP;
+   PROCESS(CLK)
+   BEGIN
+      IF(RISING_EDGE(CLK)) THEN
+         IF(RST='1') THEN
+    	    ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); 
+         ELSE
+            IF(EN='1') THEN
+               IF(LOAD='1') THEN
+	              ADDR_TEMP <=LOAD_VALUE;
+	           ELSE
+	              IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
+         	         ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
+	              ELSE
+	                 ADDR_TEMP <= ADDR_TEMP + '1';
+	              END IF;
+	           END IF;
+	        END IF;
+         END IF;
+      END IF;
+   END PROCESS;
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_stim_gen.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_stim_gen.vhd
new file mode 100755
index 000000000..6b27eacaf
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_stim_gen.vhd
@@ -0,0 +1,248 @@
+    
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_stim_gen.vhd
+--
+-- Description:
+--  Stimulus Generation For SRAM
+--  100 Writes and 100 Reads will be performed in a repeatitive loop till the 
+--  simulation ends
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY REGISTER_LOGIC_SRAM IS
+  PORT(
+       Q   : OUT STD_LOGIC;
+       CLK : IN STD_LOGIC;
+       RST : IN STD_LOGIC;
+       D   : IN STD_LOGIC
+  );
+END REGISTER_LOGIC_SRAM;
+
+ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
+   SIGNAL Q_O : STD_LOGIC :='0';
+BEGIN
+  Q <= Q_O;
+  FF_BEH: PROCESS(CLK)
+  BEGIN
+    IF(RISING_EDGE(CLK)) THEN
+      IF(RST ='1') THEN
+    	Q_O <= '0';
+      ELSE
+        Q_O <= D;
+      END IF;
+    END IF;
+  END PROCESS;
+END REGISTER_ARCH;
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+
+ENTITY BMG_STIM_GEN IS
+  PORT (
+        CLK       : IN   STD_LOGIC;
+        RST       : IN   STD_LOGIC;
+        ADDRA     : OUT  STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); 
+        DINA      : OUT  STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  
+        ENA       : OUT  STD_LOGIC :='0';
+        WEA       : OUT  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+        CHECK_DATA: OUT  STD_LOGIC:='0'
+  );
+END BMG_STIM_GEN;
+
+
+ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
+
+   CONSTANT ZERO           : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
+   SIGNAL   WRITE_ADDR     : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   SIGNAL   WRITE_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0)   := (OTHERS => '0');
+   SIGNAL   READ_ADDR_INT  : STD_LOGIC_VECTOR(12 DOWNTO 0)   := (OTHERS => '0');
+   SIGNAL   READ_ADDR      : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
+   SIGNAL   DINA_INT       : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+   SIGNAL   DO_WRITE       : STD_LOGIC                                    := '0';
+   SIGNAL   DO_READ        : STD_LOGIC                                    := '0';
+   SIGNAL   COUNT_NO       : INTEGER                                      :=0;
+   SIGNAL   DO_READ_REG    : STD_LOGIC_VECTOR(4 DOWNTO 0)                 :=(OTHERS => '0');
+   SIGNAL   WEA_VCC        : STD_LOGIC_VECTOR(3 DOWNTO 0)     :=(OTHERS => '1');
+   SIGNAL   WEA_GND        : STD_LOGIC_VECTOR(3 DOWNTO 0)     :=(OTHERS => '0');
+BEGIN
+   WRITE_ADDR_INT(12 DOWNTO 0) <= WRITE_ADDR(12 DOWNTO 0);
+   READ_ADDR_INT(12 DOWNTO 0)  <= READ_ADDR(12 DOWNTO 0);
+   ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
+    DINA  <= DINA_INT ;
+
+   CHECK_DATA <= DO_READ;
+
+RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+  GENERIC MAP( 
+    C_MAX_DEPTH => 8192 
+  )
+  PORT MAP(
+    CLK        => CLK,
+    RST        => RST,
+    EN         => DO_READ,
+    LOAD       => '0',
+    LOAD_VALUE => ZERO,
+    ADDR_OUT   => READ_ADDR
+  );
+
+WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
+  GENERIC MAP(
+    C_MAX_DEPTH => 8192  )
+  PORT MAP(
+     CLK        => CLK,
+  	 RST        => RST,
+	 EN         => DO_WRITE,
+     LOAD       => '0',
+ 	 LOAD_VALUE => ZERO,
+ 	 ADDR_OUT   => WRITE_ADDR
+  );
+
+WR_DATA_GEN_INST:ENTITY work.DATA_GEN
+   GENERIC MAP (
+     DATA_GEN_WIDTH => 32,
+     DOUT_WIDTH     => 32,
+     DATA_PART_CNT  => DATA_PART_CNT_A,
+     SEED           => 2
+   )
+   PORT MAP (
+     CLK      => CLK,
+ 	 RST      => RST,
+     EN       => DO_WRITE,
+     DATA_OUT => DINA_INT          
+   );
+
+WR_RD_PROCESS: PROCESS (CLK)
+BEGIN
+  IF(RISING_EDGE(CLK)) THEN
+     IF(RST='1') THEN
+ 	    DO_WRITE <= '0';
+        DO_READ  <= '0';
+        COUNT_NO <=  0 ;
+     ELSIF(COUNT_NO < 4) THEN
+ 	    DO_WRITE <= '1';
+        DO_READ  <= '0';
+        COUNT_NO <= COUNT_NO + 1;
+     ELSIF(COUNT_NO< 8) THEN
+	    DO_WRITE <= '0';
+        DO_READ  <= '1';
+        COUNT_NO <= COUNT_NO + 1;
+     ELSIF(COUNT_NO=8) THEN
+        DO_WRITE <= '0';
+        DO_READ  <= '0';
+        COUNT_NO <=  0 ;
+     END IF;
+  END IF;
+END PROCESS;
+
+BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
+BEGIN
+  DFF_RIGHT: IF I=0 GENERATE
+  BEGIN
+    SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
+      PORT MAP(
+        Q   => DO_READ_REG(0),
+        CLK => CLK,
+        RST => RST,
+        D   => DO_READ
+      );
+  END GENERATE DFF_RIGHT;
+  DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
+  BEGIN
+     SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
+       PORT MAP(
+          Q   => DO_READ_REG(I),
+          CLK => CLK,
+          RST => RST,
+          D   => DO_READ_REG(I-1)
+       );
+  END GENERATE DFF_OTHERS;
+END GENERATE BEGIN_SHIFT_REG;
+
+   ENA <= DO_READ OR DO_WRITE ;
+   WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_tb_pkg.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_tb_pkg.vhd
new file mode 100755
index 000000000..4928909cc
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/bmg_tb_pkg.vhd
@@ -0,0 +1,200 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Testbench Package 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bmg_tb_pkg.vhd
+--
+-- Description:
+--   BMG Testbench Package files
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+PACKAGE BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+ RETURN INTEGER;
+ ------------------------
+ FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+  RETURN STD_LOGIC_VECTOR;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STRING;
+   FALSE_CASE :STRING)
+ RETURN STRING;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : STD_LOGIC;
+   FALSE_CASE :STD_LOGIC)
+ RETURN STD_LOGIC;
+ ------------------------ 
+ FUNCTION IF_THEN_ELSE (
+   CONDITION : BOOLEAN;
+   TRUE_CASE : INTEGER;
+   FALSE_CASE : INTEGER)
+ RETURN INTEGER;
+ ------------------------ 
+ FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+ RETURN INTEGER; 
+
+END BMG_TB_PKG;
+
+PACKAGE BODY BMG_TB_PKG IS
+
+ FUNCTION DIVROUNDUP (
+    DATA_VALUE : INTEGER;
+    DIVISOR : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE DIV                   : INTEGER;
+  BEGIN
+    DIV   := DATA_VALUE/DIVISOR;
+    IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
+      DIV := DIV+1;
+    END IF;
+    RETURN DIV;
+  END DIVROUNDUP;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC_VECTOR;
+    FALSE_CASE : STD_LOGIC_VECTOR)
+    RETURN STD_LOGIC_VECTOR IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+    FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STD_LOGIC;
+    FALSE_CASE : STD_LOGIC)
+    RETURN STD_LOGIC IS
+    BEGIN
+       IF NOT CONDITION THEN
+          RETURN FALSE_CASE;
+       ELSE
+          RETURN TRUE_CASE;
+      END IF;
+   END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : INTEGER;
+    FALSE_CASE : INTEGER)
+  RETURN INTEGER IS
+    VARIABLE RETVAL : INTEGER := 0;
+  BEGIN
+    IF CONDITION=FALSE THEN
+      RETVAL:=FALSE_CASE;
+    ELSE
+      RETVAL:=TRUE_CASE;
+    END IF;
+    RETURN RETVAL;
+  END IF_THEN_ELSE;
+  ---------------------------------
+  FUNCTION IF_THEN_ELSE (
+    CONDITION : BOOLEAN;
+    TRUE_CASE : STRING;
+    FALSE_CASE : STRING)
+  RETURN STRING IS
+    BEGIN
+     IF NOT CONDITION THEN
+        RETURN FALSE_CASE;
+     ELSE
+        RETURN TRUE_CASE;
+     END IF;
+ END IF_THEN_ELSE;
+  ------------------------------- 
+  FUNCTION LOG2ROUNDUP (
+      DATA_VALUE : INTEGER)
+    RETURN INTEGER IS
+      VARIABLE WIDTH       : INTEGER := 0;
+      VARIABLE CNT         : INTEGER := 1;
+    BEGIN
+      IF (DATA_VALUE <= 1) THEN
+        WIDTH   := 1;
+      ELSE
+        WHILE (CNT < DATA_VALUE) LOOP
+          WIDTH := WIDTH + 1;
+          CNT   := CNT *2;
+        END LOOP;
+      END IF;
+      RETURN WIDTH;
+    END LOG2ROUNDUP;
+
+END BMG_TB_PKG;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_synth.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_synth.vhd
new file mode 100755
index 000000000..13d6bd168
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_synth.vhd
@@ -0,0 +1,296 @@
+ 
+ 
+ 
+
+ 
+
+
+
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: bootram_synth.vhd
+--
+-- Description:
+--  Synthesizable Testbench
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.STD_LOGIC_MISC.ALL;
+
+LIBRARY STD;
+USE STD.TEXTIO.ALL;
+
+--LIBRARY unisim;
+--USE unisim.vcomponents.ALL;
+
+LIBRARY work;
+USE work.ALL;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY bootram_synth IS
+PORT(
+	CLK_IN     : IN  STD_LOGIC;
+    RESET_IN   : IN  STD_LOGIC;
+    STATUS     : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0')   --ERROR STATUS OUT OF FPGA
+    );
+END ENTITY;
+
+ARCHITECTURE bootram_synth_ARCH OF bootram_synth IS
+
+
+COMPONENT bootram_exdes 
+  PORT (
+      --Inputs - Port A
+    ENA            : IN STD_LOGIC;  --opt port
+    WEA            : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    ADDRA          : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
+    DINA           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    DOUTA          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    CLKA       : IN STD_LOGIC
+
+
+  );
+
+END COMPONENT;
+
+
+  SIGNAL CLKA: STD_LOGIC := '0';
+  SIGNAL RSTA: STD_LOGIC := '0';
+  SIGNAL ENA: STD_LOGIC := '0';
+  SIGNAL ENA_R: STD_LOGIC := '0';
+  SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL CHECKER_EN : STD_LOGIC:='0';
+  SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
+  SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
+  SIGNAL clk_in_i: STD_LOGIC;
+ 
+  SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
+  SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
+
+  SIGNAL ITER_R0 : STD_LOGIC := '0';
+  SIGNAL ITER_R1 : STD_LOGIC := '0';
+  SIGNAL ITER_R2 : STD_LOGIC := '0';
+
+  SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+  SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+
+  BEGIN
+
+--  clk_buf: bufg
+--    PORT map(
+--      i => CLK_IN,
+--      o => clk_in_i
+--    );
+   clk_in_i <= CLK_IN;
+   CLKA <= clk_in_i;
+
+   RSTA <= RESET_SYNC_R3 AFTER 50 ns;
+
+
+   PROCESS(clk_in_i)
+   BEGIN
+      IF(RISING_EDGE(clk_in_i)) THEN
+		 RESET_SYNC_R1 <= RESET_IN;
+		 RESET_SYNC_R2 <= RESET_SYNC_R1;
+		 RESET_SYNC_R3 <= RESET_SYNC_R2;
+	  END IF;
+   END PROCESS;
+
+
+PROCESS(CLKA)
+BEGIN
+  IF(RISING_EDGE(CLKA)) THEN
+    IF(RESET_SYNC_R3='1') THEN
+        ISSUE_FLAG_STATUS<= (OTHERS => '0'); 
+	  ELSE
+        ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
+   END IF;
+  END IF;
+END PROCESS;
+
+STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
+
+
+
+   BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
+      GENERIC MAP ( 
+         WRITE_WIDTH => 32,
+		 READ_WIDTH  => 32      )
+      PORT MAP (
+         CLK     => CLKA,
+         RST     => RSTA, 
+         EN      => CHECKER_EN_R,
+         DATA_IN => DOUTA,
+         STATUS  => ISSUE_FLAG(0)
+	   );
+
+   PROCESS(CLKA)
+   BEGIN
+      IF(RISING_EDGE(CLKA)) THEN
+         IF(RSTA='1') THEN
+		    CHECKER_EN_R <= '0';
+	     ELSE
+		    CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+    BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
+     PORT MAP(
+                CLK => clk_in_i,
+             	RST => RSTA,
+                ADDRA  => ADDRA,
+                DINA => DINA,
+ 
+                ENA => ENA,
+                WEA => WEA,
+	            CHECK_DATA => CHECKER_EN
+             );
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+			STATUS(8) <= '0';
+			iter_r2 <= '0';
+			iter_r1 <= '0';
+			iter_r0 <= '0';
+		  ELSE
+			STATUS(8) <= iter_r2;
+			iter_r2 <= iter_r1;
+			iter_r1 <= iter_r0;
+			iter_r0 <= STIMULUS_FLOW(8);
+	      END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+		      STIMULUS_FLOW <= (OTHERS => '0'); 
+           ELSIF(WEA(0)='1') THEN
+		      STIMULUS_FLOW <= STIMULUS_FLOW+1;
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+            ENA_R <= '0' AFTER 50 ns;
+            WEA_R  <= (OTHERS=>'0') AFTER 50 ns;
+            DINA_R <= (OTHERS=>'0') AFTER 50 ns;
+          
+
+           ELSE
+          ENA_R <= ENA AFTER 50 ns;
+            WEA_R  <= WEA AFTER 50 ns;
+            DINA_R <= DINA AFTER 50 ns;
+
+         END IF;
+	    END IF;
+      END PROCESS;
+
+
+      PROCESS(CLKA)
+      BEGIN
+        IF(RISING_EDGE(CLKA)) THEN
+		  IF(RESET_SYNC_R3='1') THEN
+            ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
+          ELSE
+            ADDRA_R <= ADDRA AFTER 50 ns;
+          END IF;
+	    END IF;
+      END PROCESS;
+
+
+    BMG_PORT: bootram_exdes PORT MAP ( 
+      --Port A
+      ENA        => ENA_R,
+      WEA        => WEA_R,
+      ADDRA      => ADDRA_R,
+      DINA       => DINA_R,
+      DOUTA      => DOUTA,
+      CLKA       => CLKA
+
+    );
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_tb.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_tb.vhd
new file mode 100755
index 000000000..5cb67cd60
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/bootram_tb.vhd
@@ -0,0 +1,134 @@
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+-- Filename: bootram_tb.vhd
+-- Description:
+--  Testbench Top
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.ALL;
+
+ENTITY bootram_tb IS
+END ENTITY;
+
+
+ARCHITECTURE bootram_tb_ARCH OF bootram_tb IS
+ SIGNAL  STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
+ SIGNAL  CLK :  STD_LOGIC := '1';
+ SIGNAL  RESET : STD_LOGIC;
+ 
+ BEGIN
+
+  
+ CLK_GEN: PROCESS BEGIN
+     CLK <= NOT CLK;
+     WAIT FOR 100 NS;
+     CLK <= NOT CLK; 
+     WAIT FOR 100 NS;
+  END PROCESS;
+  
+  RST_GEN: PROCESS BEGIN
+    RESET <= '1';
+    WAIT FOR 1000 NS;
+    RESET <= '0';
+    WAIT;
+  END PROCESS;
+
+  
+--STOP_SIM: PROCESS BEGIN
+-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
+--   ASSERT FALSE
+--     REPORT "END SIMULATION TIME REACHED"
+--     SEVERITY FAILURE;
+--END PROCESS;
+--
+PROCESS BEGIN
+  WAIT UNTIL STATUS(8)='1';
+  IF( STATUS(7 downto 0)/="0") THEN
+    ASSERT false
+     REPORT "Test Completed Successfully"
+	 SEVERITY NOTE;
+     REPORT "Simulation Failed"
+	 SEVERITY FAILURE;
+  ELSE
+   ASSERT false
+     REPORT "TEST PASS"
+     SEVERITY NOTE;
+     REPORT "Test Completed Successfully"
+	 SEVERITY FAILURE;
+  END IF;
+  
+END PROCESS;	 
+  
+  bootram_synth_inst:ENTITY work.bootram_synth
+  PORT MAP(
+           CLK_IN   => CLK,
+     	   RESET_IN => RESET,
+           STATUS   => STATUS
+	  );
+
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/checker.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/checker.vhd
new file mode 100755
index 000000000..15a275385
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/checker.vhd
@@ -0,0 +1,161 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Checker
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: checker.vhd
+--
+-- Description:
+--   Checker
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY CHECKER IS
+  GENERIC ( WRITE_WIDTH : INTEGER :=32;
+            READ_WIDTH  : INTEGER :=32
+  );
+        
+  PORT (
+        CLK      : IN STD_LOGIC;
+        RST      : IN STD_LOGIC;
+        EN       : IN STD_LOGIC; 
+        DATA_IN  : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0);   --OUTPUT VECTOR          
+        STATUS   : OUT STD_LOGIC:= '0'
+  );
+END CHECKER;
+
+ARCHITECTURE CHECKER_ARCH OF CHECKER IS
+  SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+  SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
+  SIGNAL EN_R : STD_LOGIC := '0';
+  SIGNAL EN_2R : STD_LOGIC := '0';
+--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
+--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
+--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
+  CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
+  CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
+  SIGNAL ERR_HOLD : STD_LOGIC :='0';
+  SIGNAL ERR_DET : STD_LOGIC :='0';
+BEGIN
+   PROCESS(CLK)
+   BEGIN
+     IF(RISING_EDGE(CLK)) THEN
+       IF(RST= '1') THEN
+     	  EN_R <= '0';
+     	  EN_2R <= '0';
+          DATA_IN_R <= (OTHERS=>'0');
+       ELSE
+	      EN_R <= EN;
+	      EN_2R <= EN_R;
+          DATA_IN_R <= DATA_IN;
+       END IF;        
+     END IF;
+   END PROCESS;
+
+   EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN 
+      GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
+                    DOUT_WIDTH     => READ_WIDTH,
+         		    DATA_PART_CNT  => DATA_PART_CNT,
+	                SEED           => 2
+      )
+      PORT MAP (
+            CLK      => CLK,
+			RST      => RST,
+            EN       => EN_2R,
+            DATA_OUT => EXPECTED_DATA
+	  );
+
+   PROCESS(CLK)
+   BEGIN
+      IF(RISING_EDGE(CLK)) THEN
+         IF(EN_2R='1') THEN
+        	 IF(EXPECTED_DATA = DATA_IN_R) THEN
+	            ERR_DET<='0';
+        	 ELSE
+	            ERR_DET<= '1';
+        	 END IF;
+         END IF;
+     END IF;
+   END PROCESS;
+
+   PROCESS(CLK,RST)
+   BEGIN
+	  IF(RST='1') THEN
+		 ERR_HOLD <= '0';
+      ELSIF(RISING_EDGE(CLK)) THEN
+         ERR_HOLD <= ERR_HOLD  OR ERR_DET ;
+      END IF;
+   END PROCESS;
+
+   STATUS <= ERR_HOLD;
+
+END ARCHITECTURE;
+
+
+
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/data_gen.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/data_gen.vhd
new file mode 100755
index 000000000..fe3dca7e5
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/data_gen.vhd
@@ -0,0 +1,140 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Data Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: data_gen.vhd
+--
+-- Description:
+--   Data Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+LIBRARY work;
+USE work.BMG_TB_PKG.ALL;
+
+ENTITY DATA_GEN IS
+  GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
+            DOUT_WIDTH     : INTEGER := 32;
+            DATA_PART_CNT  : INTEGER := 1;
+            SEED           : INTEGER := 2
+  );
+        
+  PORT (
+        CLK      : IN STD_LOGIC;
+        RST      : IN STD_LOGIC;
+        EN       : IN STD_LOGIC; 
+        DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END DATA_GEN;
+
+ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
+  CONSTANT LOOP_COUNT     : INTEGER   := DIVROUNDUP(DATA_GEN_WIDTH,8);
+  SIGNAL   RAND_DATA      : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+  SIGNAL   LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
+  SIGNAL   LOCAL_CNT      : INTEGER   :=1;
+  SIGNAL   DATA_GEN_I     : STD_LOGIC :='0';
+BEGIN
+
+  LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
+  DATA_OUT       <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
+  DATA_GEN_I     <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
+
+  PROCESS(CLK)
+  BEGIN
+     IF(RISING_EDGE (CLK)) THEN
+        IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
+           LOCAL_CNT <=1;
+        ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
+           IF(LOCAL_CNT = 1) THEN
+              LOCAL_CNT <= LOCAL_CNT+1;
+           ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
+              LOCAL_CNT <= LOCAL_CNT+1;
+           ELSE
+              LOCAL_CNT <= 1;
+           END IF;
+        ELSE
+          LOCAL_CNT <= 1;
+        END IF;
+     END IF;
+  END PROCESS;
+
+  RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+    RAND_GEN_INST:ENTITY work.RANDOM
+       GENERIC MAP(
+           WIDTH => 8,
+           SEED => (SEED+N) 
+       )
+       PORT MAP(
+          CLK => CLK,
+	      RST => RST,
+          EN  => DATA_GEN_I,
+          RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
+       );
+  END GENERATE RAND_GEN;
+
+END ARCHITECTURE;
+
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl
new file mode 100755
index 000000000..212a904f5
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl
@@ -0,0 +1,64 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+ 
+
+
+
+wcfg new
+isim set radix hex
+wave add /bootram_tb/status
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/CLKA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ADDRA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DINA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/WEA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ENA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DOUTA
+run all
+quit
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh
new file mode 100755
index 000000000..0768d7b5f
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh
@@ -0,0 +1,71 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+cp ../../../bootram.mif .
+
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogcomp -work work ../../../bootram.v 
+vhpcomp -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ../bmg_tb_pkg.vhd
+vhpcomp -work work    ../random.vhd
+vhpcomp -work work    ../data_gen.vhd
+vhpcomp -work work    ../addr_gen.vhd
+vhpcomp -work work    ../checker.vhd
+vhpcomp -work work    ../bmg_stim_gen.vhd
+vhpcomp -work work    ../bootram_synth.vhd 
+vhpcomp -work work    ../bootram_tb.vhd
+
+
+vlogcomp -work work $XILINX/verilog/src/glbl.v
+fuse work.bootram_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o bootram_tb.exe
+
+./bootram_tb.exe -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat
new file mode 100755
index 000000000..5964f52d7
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do
new file mode 100755
index 000000000..ba3c8ef12
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do
@@ -0,0 +1,77 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+ vlib work 
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../../bootram.v 
+vcom -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../random.vhd
+vcom -work work    ../data_gen.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../checker.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../bootram_synth.vhd 
+vcom -work work    ../bootram_tb.vhd
+
+
+vlog -work work $env(XILINX)/verilog/src/glbl.v
+vsim  -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.bootram_tb
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh
new file mode 100755
index 000000000..5964f52d7
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh
new file mode 100755
index 000000000..eabc07d61
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh
@@ -0,0 +1,72 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+
+
+mkdir work
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+ncvlog -work work ../../../bootram.v 
+ncvhdl -v93 -work work ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../random.vhd
+ncvhdl -v93 -work work    ../data_gen.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../checker.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../bootram_synth.vhd 
+ncvhdl -v93 -work work    ../bootram_tb.vhd
+
+echo "Elaborating Design"
+ncvlog -work work $XILINX/verilog/src/glbl.v
+ncelab -access +rwc glbl work.bootram_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" work.bootram_tb
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh
new file mode 100755
index 000000000..0eff1c3fe
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh
@@ -0,0 +1,71 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../bootram.mif .
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../../bootram.v
+vhdlan  ../../example_design/bootram_exdes.vhd
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../random.vhd
+vhdlan    ../data_gen.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../checker.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../bootram_synth.vhd 
+vhdlan    ../bootram_tb.vhd
+
+echo "Elaborating Design"
+vlogan +v2k $XILINX/verilog/src/glbl.v
+vcs +vcs+lic+wait -debug bootram_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key
new file mode 100755
index 000000000..358a13b79
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add bootram_tb
+run 
+quit
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl
new file mode 100755
index 000000000..b55991252
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl
@@ -0,0 +1,84 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#--  BMG core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create bootram_Group
+gui_list_add_group -id Wave.1 {bootram_Group}
+
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/status
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do
new file mode 100755
index 000000000..13844e041
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do
@@ -0,0 +1,37 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+      add wave -noupdate /bootram_tb/status
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 197
+configure wave -valuecolwidth 106
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv
new file mode 100755
index 000000000..6e51f9989
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv
@@ -0,0 +1,22 @@
+
+
+ 
+ 
+ 
+
+ 
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+      waveform add -signals /bootram_tb/status
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+console submit -using simulator -wait no "run"
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/random.vhd b/fpga/usrp3/top/x300/coregen/bootram/simulation/random.vhd
new file mode 100755
index 000000000..b0d417cbe
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/random.vhd
@@ -0,0 +1,112 @@
+
+--------------------------------------------------------------------------------
+--
+-- BLK MEM GEN v7_3 Core - Random Number Generator
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+
+--------------------------------------------------------------------------------
+--
+-- Filename: random.vhd
+--
+-- Description:
+--   Random Generator
+--
+--------------------------------------------------------------------------------
+-- Author: IP Solutions Division
+--
+-- History: Sep 12, 2011 - First Release
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+ENTITY RANDOM IS
+  GENERIC ( WIDTH : INTEGER :=  32;
+ 	        SEED  : INTEGER :=2 
+  );
+        
+  PORT (
+     CLK        : IN STD_LOGIC;
+     RST        : IN STD_LOGIC;
+     EN         : IN STD_LOGIC;
+     RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
+  );
+END RANDOM;
+
+ARCHITECTURE BEHAVIORAL OF RANDOM IS
+BEGIN
+  PROCESS(CLK)
+    VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+    VARIABLE TEMP      : STD_LOGIC := '0';
+  BEGIN
+    IF(RISING_EDGE(CLK)) THEN
+       IF(RST='1') THEN
+          RAND_TEMP  := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
+	   ELSE
+          IF(EN = '1') THEN
+             TEMP                        := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
+             RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
+             RAND_TEMP(0)                := TEMP;
+          END IF;
+       END IF;
+    END IF;
+    RANDOM_NUM <= RAND_TEMP;
+  END PROCESS;
+END ARCHITECTURE;
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simcmds.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simcmds.tcl
new file mode 100755
index 000000000..212a904f5
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simcmds.tcl
@@ -0,0 +1,64 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+ 
+ 
+ 
+
+ 
+
+
+
+wcfg new
+isim set radix hex
+wave add /bootram_tb/status
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/CLKA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ADDRA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DINA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/WEA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/ENA
+      wave add  /bootram_tb/bootram_synth_inst/BMG_PORT/DOUTA
+run all
+quit
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_isim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_isim.sh
new file mode 100755
index 000000000..03a0b167a
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_isim.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+
+cp ../../../bootram.mif .
+
+
+vlogcomp -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+vhpcomp -work work    ../bmg_tb_pkg.vhd
+vhpcomp -work work    ../random.vhd
+vhpcomp -work work    ../data_gen.vhd
+vhpcomp -work work    ../addr_gen.vhd
+vhpcomp -work work    ../checker.vhd
+vhpcomp -work work    ../bmg_stim_gen.vhd
+vhpcomp -work work    ../bootram_synth.vhd 
+vhpcomp -work work    ../bootram_tb.vhd
+
+    fuse -L simprims_ver work.bootram_tb work.glbl -o bootram_tb.exe
+
+./bootram_tb.exe -sdftyp /bootram_tb/bootram_synth_inst/bmg_port=../../implement/results/routed.sdf -gui -tclbatch simcmds.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.bat b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.bat
new file mode 100755
index 000000000..5964f52d7
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.bat
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.do
new file mode 100755
index 000000000..d77990599
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.do
@@ -0,0 +1,76 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+
+vlib work
+vmap work work
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+vcom -work work    ../bmg_tb_pkg.vhd
+vcom -work work    ../random.vhd
+vcom -work work    ../data_gen.vhd
+vcom -work work    ../addr_gen.vhd
+vcom -work work    ../checker.vhd
+vcom -work work    ../bmg_stim_gen.vhd
+vcom -work work    ../bootram_synth.vhd 
+vcom -work work    ../bootram_tb.vhd
+
+    vsim -novopt -t ps  -L simprims_ver +transport_int_delays -sdftyp /bootram_tb/bootram_synth_inst/bmg_port=../../implement/results/routed.sdf $work.bootram_tb $work.glbl -novopt
+
+#Disabled waveform to save the disk space
+add log -r /*
+#Ignore integer warnings at time 0
+set StdArithNoWarnings 1
+run 0
+set StdArithNoWarnings 0
+
+run -all
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.sh
new file mode 100755
index 000000000..5964f52d7
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_mti.sh
@@ -0,0 +1,3 @@
+#--------------------------------------------------------------------------------
+
+vsim -c -do simulate_mti.do
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_ncsim.sh
new file mode 100755
index 000000000..9c78ee646
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_ncsim.sh
@@ -0,0 +1,79 @@
+#!/bin/sh
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+set work work
+#--------------------------------------------------------------------------------
+cp ../../../bootram.mif .
+mkdir work
+
+
+ncvlog -work work ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+
+ncvhdl -v93 -work work    ../bmg_tb_pkg.vhd
+ncvhdl -v93 -work work    ../random.vhd
+ncvhdl -v93 -work work    ../data_gen.vhd
+ncvhdl -v93 -work work    ../addr_gen.vhd
+ncvhdl -v93 -work work    ../checker.vhd
+ncvhdl -v93 -work work    ../bmg_stim_gen.vhd
+ncvhdl -v93 -work work    ../bootram_synth.vhd 
+ncvhdl -v93 -work work    ../bootram_tb.vhd
+
+echo "Compiling SDF file"
+ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X
+
+echo "Generating SDF command file"
+echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd
+echo 'SCOPE = :bootram_synth_inst:BMG_PORT,' >> sdf.cmd
+echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd
+
+
+echo "Elaborating Design"
+ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.bootram_tb
+
+echo "Simulating Design"
+ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.bootram_tb
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_vcs.sh
new file mode 100755
index 000000000..0454ba14d
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/simulate_vcs.sh
@@ -0,0 +1,71 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#--------------------------------------------------------------------------------
+#!/bin/sh
+cp ../../../bootram.mif .
+
+rm -rf simv* csrc DVEfiles AN.DB
+
+echo "Compiling Core Verilog UNISIM/Behavioral model"
+vlogan +v2k  ../../implement/results/routed.v
+
+echo "Compiling Test Bench Files"
+vhdlan    ../bmg_tb_pkg.vhd
+vhdlan    ../random.vhd
+vhdlan    ../data_gen.vhd
+vhdlan    ../addr_gen.vhd
+vhdlan    ../checker.vhd
+vhdlan    ../bmg_stim_gen.vhd
+vhdlan    ../bootram_synth.vhd 
+vhdlan    ../bootram_tb.vhd
+
+
+echo "Elaborating Design"
+vcs +neg_tchk +vcs+lic+wait -debug bootram_tb glbl
+
+echo "Simulating Design"
+./simv -ucli -i ucli_commands.key
+dve -session vcs_session.tcl
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/ucli_commands.key b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/ucli_commands.key
new file mode 100755
index 000000000..358a13b79
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/ucli_commands.key
@@ -0,0 +1,4 @@
+dump -file bmg_vcs.vpd -type VPD
+dump -add bootram_tb
+run 
+quit
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/vcs_session.tcl
new file mode 100755
index 000000000..9d061e1a6
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/vcs_session.tcl
@@ -0,0 +1,84 @@
+ 
+ 
+ 
+
+ 
+
+
+
+#--------------------------------------------------------------------------------
+#--
+#-- BMG Generator v8.4 Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } {
+	gui_open_db -design V1 -file bmg_vcs.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+gui_open_window Wave
+gui_sg_create bootram_Group
+gui_list_add_group -id Wave.1 {bootram_Group}
+
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/status
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      gui_sg_addsignal -group bootram_Group  /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+
+gui_zoom -window Wave.1 -full
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_mti.do
new file mode 100755
index 000000000..30c5a09af
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_mti.do
@@ -0,0 +1,37 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+
+
+      add wave -noupdate /bootram_tb/status
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {9464063 ps}
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_ncsim.sv
new file mode 100755
index 000000000..3eec6a517
--- /dev/null
+++ b/fpga/usrp3/top/x300/coregen/bootram/simulation/timing/wave_ncsim.sv
@@ -0,0 +1,21 @@
+
+ 
+ 
+ 
+
+ 
+
+
+
+window new WaveWindow  -name  "Waves for BMG Example Design"
+waveform  using  "Waves for BMG Example Design"
+
+
+      waveform add -signals /bootram_tb/status
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/CLKA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ADDRA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DINA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/WEA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ENA
+      waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DOUTA
+console submit -using simulator -wait no "run"