diff options
| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/top/x300/bus_int_tb.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/top/x300/bus_int_tb.v')
| -rw-r--r-- | fpga/usrp3/top/x300/bus_int_tb.v | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/fpga/usrp3/top/x300/bus_int_tb.v b/fpga/usrp3/top/x300/bus_int_tb.v deleted file mode 100644 index 70103c3bf..000000000 --- a/fpga/usrp3/top/x300/bus_int_tb.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns/1ps - -module bus_int_tb(); - - wire GSR, GTS; - xlnx_glbl glbl( ); - - reg clk = 0; - reg reset = 1; - - always #10 clk = ~clk; - - initial $dumpfile("bus_int_tb.vcd"); - initial $dumpvars(0,bus_int_tb); - - initial - begin - #1000 reset = 0; - #2000000; - $finish; - end - - wire sen, sclk, mosi, miso; - wire scl, sda; - - bus_int bus_int - (.clk(clk), .reset(reset), - .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso), - .scl(scl), .sda(sda) - ); - -endmodule // bus_int_tb |